// Generated by FIR Compiler
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module fir_ssb_st (clk, 
              rst, 
              data_in, 
              clk_en, 
              rdy_to_ld, 
              done, 
              fir_result); 
parameter DATA_WIDTH  = 14;
parameter COEF_WIDTH  = 8;
parameter ACCUM_WIDTH = 27;

input clk, rst;
input [DATA_WIDTH-1:0] data_in;
input clk_en;
output rdy_to_ld;
wire rdy_to_ld;
wire rdy_int;
wire data_ld;
output done;
wire done;
wire done_int;
output [ACCUM_WIDTH-1:0] fir_result;
wire addr_low;
assign addr_low = 1'b0;


//--- Parallel TDL Storage ---
wire inv_rst;
assign inv_rst = ~rst;
assign data_ld = rdy_int;
wire [13:0] tdl_0_n;
wire [13:0] tdl_1_n;
wire [13:0] tdl_2_n;
wire [13:0] tdl_3_n;
wire [13:0] tdl_4_n;
wire [13:0] tdl_5_n;
wire [13:0] tdl_6_n;
wire [13:0] tdl_7_n;
wire [13:0] tdl_8_n;
wire [13:0] tdl_9_n;
wire [13:0] tdl_10_n;
wire [13:0] tdl_11_n;
wire [13:0] tdl_12_n;
wire [13:0] tdl_13_n;
wire [13:0] tdl_14_n;
wire [13:0] tdl_15_n;
wire [13:0] tdl_16_n;
wire [13:0] tdl_17_n;
wire [13:0] tdl_18_n;
wire [13:0] tdl_19_n;
wire [13:0] tdl_20_n;
wire [13:0] tdl_21_n;


//--- TDL  ---
tdl_da_lc Utdldalc0n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(data_in), .data_out(tdl_0_n) );
defparam Utdldalc0n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc1n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_0_n), .data_out(tdl_1_n) );
defparam Utdldalc1n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc2n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_1_n), .data_out(tdl_2_n) );
defparam Utdldalc2n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc3n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_2_n), .data_out(tdl_3_n) );
defparam Utdldalc3n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc4n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_3_n), .data_out(tdl_4_n) );
defparam Utdldalc4n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc5n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_4_n), .data_out(tdl_5_n) );
defparam Utdldalc5n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc6n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_5_n), .data_out(tdl_6_n) );
defparam Utdldalc6n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc7n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_6_n), .data_out(tdl_7_n) );
defparam Utdldalc7n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc8n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_7_n), .data_out(tdl_8_n) );
defparam Utdldalc8n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc9n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_8_n), .data_out(tdl_9_n) );
defparam Utdldalc9n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc10n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_9_n), .data_out(tdl_10_n) );
defparam Utdldalc10n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc11n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_10_n), .data_out(tdl_11_n) );
defparam Utdldalc11n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc12n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_11_n), .data_out(tdl_12_n) );
defparam Utdldalc12n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc13n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_12_n), .data_out(tdl_13_n) );
defparam Utdldalc13n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc14n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_13_n), .data_out(tdl_14_n) );
defparam Utdldalc14n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc15n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_14_n), .data_out(tdl_15_n) );
defparam Utdldalc15n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc16n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_15_n), .data_out(tdl_16_n) );
defparam Utdldalc16n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc17n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_16_n), .data_out(tdl_17_n) );
defparam Utdldalc17n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc18n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_17_n), .data_out(tdl_18_n) );
defparam Utdldalc18n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc19n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_18_n), .data_out(tdl_19_n) );
defparam Utdldalc19n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc20n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_19_n), .data_out(tdl_20_n) );
defparam Utdldalc20n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc21n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_20_n), .data_out(tdl_21_n) );
defparam Utdldalc21n.WIDTH = DATA_WIDTH;


// --- ROM LUTs ---- 
// symmetrical adders ...
wire [14:0] sym_res_0_n;
sadd_cen U_0_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_0_n), .bin(tdl_21_n), .res(sym_res_0_n) );
defparam U_0_sym_add.IN_WIDTH = 14;
defparam U_0_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_1_n;
sadd_cen U_1_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_1_n), .bin(tdl_20_n), .res(sym_res_1_n) );
defparam U_1_sym_add.IN_WIDTH = 14;
defparam U_1_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_2_n;
sadd_cen U_2_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_2_n), .bin(tdl_19_n), .res(sym_res_2_n) );
defparam U_2_sym_add.IN_WIDTH = 14;
defparam U_2_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_3_n;
sadd_cen U_3_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_3_n), .bin(tdl_18_n), .res(sym_res_3_n) );
defparam U_3_sym_add.IN_WIDTH = 14;
defparam U_3_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_4_n;
sadd_cen U_4_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_4_n), .bin(tdl_17_n), .res(sym_res_4_n) );
defparam U_4_sym_add.IN_WIDTH = 14;
defparam U_4_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_5_n;
sadd_cen U_5_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_5_n), .bin(tdl_16_n), .res(sym_res_5_n) );
defparam U_5_sym_add.IN_WIDTH = 14;
defparam U_5_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_6_n;
sadd_cen U_6_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_6_n), .bin(tdl_15_n), .res(sym_res_6_n) );
defparam U_6_sym_add.IN_WIDTH = 14;
defparam U_6_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_7_n;
sadd_cen U_7_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_7_n), .bin(tdl_14_n), .res(sym_res_7_n) );
defparam U_7_sym_add.IN_WIDTH = 14;
defparam U_7_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_8_n;
sadd_cen U_8_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_8_n), .bin(tdl_13_n), .res(sym_res_8_n) );
defparam U_8_sym_add.IN_WIDTH = 14;
defparam U_8_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_9_n;
sadd_cen U_9_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_9_n), .bin(tdl_12_n), .res(sym_res_9_n) );
defparam U_9_sym_add.IN_WIDTH = 14;
defparam U_9_sym_add.PIPE_DEPTH = 1;
wire [14:0] sym_res_10_n;
sadd_cen U_10_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_10_n), .bin(tdl_11_n), .res(sym_res_10_n) );
defparam U_10_sym_add.IN_WIDTH = 14;
defparam U_10_sym_add.PIPE_DEPTH = 1;


wire [9:0] lut_val_0_n_0_pp;
rom_lut_r_cen Ur0_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[0],sym_res_2_n[0],sym_res_1_n[0],sym_res_0_n[0] } ), .data_out( lut_val_0_n_0_pp[6:0]) ) ;
 defparam Ur0_n_0_pp.DATA_WIDTH = 7;
defparam Ur0_n_0_pp.C0 =                    0;
defparam Ur0_n_0_pp.C1 =                    5;
defparam Ur0_n_0_pp.C2 =                  121;
defparam Ur0_n_0_pp.C3 =                  126;
defparam Ur0_n_0_pp.C4 =                  109;
defparam Ur0_n_0_pp.C5 =                  114;
defparam Ur0_n_0_pp.C6 =                  102;
defparam Ur0_n_0_pp.C7 =                  107;
defparam Ur0_n_0_pp.C8 =                  101;
defparam Ur0_n_0_pp.C9 =                  106;
defparam Ur0_n_0_pp.CA =                   94;
defparam Ur0_n_0_pp.CB =                   99;
defparam Ur0_n_0_pp.CC =                   82;
defparam Ur0_n_0_pp.CD =                   87;
defparam Ur0_n_0_pp.CE =                   75;
defparam Ur0_n_0_pp.CF =                   80;
assign lut_val_0_n_0_pp[9] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[8] = lut_val_0_n_0_pp[6];
assign lut_val_0_n_0_pp[7] = lut_val_0_n_0_pp[6];
wire [9:0] lut_val_0_n_1_pp;
rom_lut_r_cen Ur0_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[1],sym_res_2_n[1],sym_res_1_n[1],sym_res_0_n[1] } ), .data_out( lut_val_0_n_1_pp[6:0]) ) ;
 defparam Ur0_n_1_pp.DATA_WIDTH = 7;
defparam Ur0_n_1_pp.C0 =                    0;
defparam Ur0_n_1_pp.C1 =                    5;
defparam Ur0_n_1_pp.C2 =                  121;
defparam Ur0_n_1_pp.C3 =                  126;
defparam Ur0_n_1_pp.C4 =                  109;
defparam Ur0_n_1_pp.C5 =                  114;
defparam Ur0_n_1_pp.C6 =                  102;
defparam Ur0_n_1_pp.C7 =                  107;
defparam Ur0_n_1_pp.C8 =                  101;
defparam Ur0_n_1_pp.C9 =                  106;
defparam Ur0_n_1_pp.CA =                   94;
defparam Ur0_n_1_pp.CB =                   99;
defparam Ur0_n_1_pp.CC =                   82;
defparam Ur0_n_1_pp.CD =                   87;
defparam Ur0_n_1_pp.CE =                   75;
defparam Ur0_n_1_pp.CF =                   80;
assign lut_val_0_n_1_pp[9] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[8] = lut_val_0_n_1_pp[6];
assign lut_val_0_n_1_pp[7] = lut_val_0_n_1_pp[6];
wire [9:0] lut_val_0_n_2_pp;
rom_lut_r_cen Ur0_n_2_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[2],sym_res_2_n[2],sym_res_1_n[2],sym_res_0_n[2] } ), .data_out( lut_val_0_n_2_pp[6:0]) ) ;
 defparam Ur0_n_2_pp.DATA_WIDTH = 7;
defparam Ur0_n_2_pp.C0 =                    0;
defparam Ur0_n_2_pp.C1 =                    5;
defparam Ur0_n_2_pp.C2 =                  121;
defparam Ur0_n_2_pp.C3 =                  126;
defparam Ur0_n_2_pp.C4 =                  109;
defparam Ur0_n_2_pp.C5 =                  114;
defparam Ur0_n_2_pp.C6 =                  102;
defparam Ur0_n_2_pp.C7 =                  107;
defparam Ur0_n_2_pp.C8 =                  101;
defparam Ur0_n_2_pp.C9 =                  106;
defparam Ur0_n_2_pp.CA =                   94;
defparam Ur0_n_2_pp.CB =                   99;
defparam Ur0_n_2_pp.CC =                   82;
defparam Ur0_n_2_pp.CD =                   87;
defparam Ur0_n_2_pp.CE =                   75;
defparam Ur0_n_2_pp.CF =                   80;
assign lut_val_0_n_2_pp[9] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[8] = lut_val_0_n_2_pp[6];
assign lut_val_0_n_2_pp[7] = lut_val_0_n_2_pp[6];
wire [9:0] lut_val_0_n_3_pp;
rom_lut_r_cen Ur0_n_3_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_3_n[3],sym_res_2_n[3],sym_res_1_n[3],sym_res_0_n[3] } ), .data_out( lut_val_0_n_3_pp[6:0]) ) ;
 defparam Ur0_n_3_pp.DATA_WIDTH = 7;