?? ask_mod.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" { } { { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } { "f:/program files/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register memory nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\] nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0 216.08 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 216.08 MHz between source register \"nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\]\" and destination memory \"nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.314 ns 2.314 ns 4.628 ns " "Info: fmax restricted to Clock High delay (2.314 ns) plus Clock Low delay (2.314 ns) : restricted to 4.628 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.741 ns + Longest register memory " "Info: + Longest register to memory delay is 3.741 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\] 1 REG LCFF_X19_Y11_N21 52 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y11_N21; Fanout = 52; REG Node = 'nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\]'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } "NODE_NAME" } } { "../../../ip/nco/lib/asj_gar.v" "" { Text "F:/program files/altera/61/ip/nco/lib/asj_gar.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.582 ns) + CELL(0.159 ns) 3.741 ns nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0 2 MEM M4K_X52_Y22 1 " "Info: 2: + IC(3.582 ns) + CELL(0.159 ns) = 3.741 ns; Loc. = M4K_X52_Y22; Fanout = 1; MEM Node = 'nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.741 ns" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jq81.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/altsyncram_jq81.tdf" 364 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.159 ns ( 4.25 % ) " "Info: Total cell delay = 0.159 ns ( 4.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.582 ns ( 95.75 % ) " "Info: Total interconnect delay = 3.582 ns ( 95.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.741 ns" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.741 ns" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 3.582ns } { 0.000ns 0.159ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.093 ns - Smallest " "Info: - Smallest clock skew is 0.093 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.990 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 2480 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 2480; COMB Node = 'clock~clkctrl'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.747 ns) 2.990 ns nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0 3 MEM M4K_X52_Y22 1 " "Info: 3: + IC(1.028 ns) + CELL(0.747 ns) = 2.990 ns; Loc. = M4K_X52_Y22; Fanout = 1; MEM Node = 'nco1:inst1\|nco1_st:nco1_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_jq81:auto_generated\|ram_block1a15~porta_address_reg0'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.775 ns" { clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jq81.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/altsyncram_jq81.tdf" 364 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.783 ns ( 59.63 % ) " "Info: Total cell delay = 1.783 ns ( 59.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.207 ns ( 40.37 % ) " "Info: Total interconnect delay = 1.207 ns ( 40.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.990 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.990 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 0.000ns 0.179ns 1.028ns } { 0.000ns 1.036ns 0.000ns 0.747ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.897 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 2480 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 2480; COMB Node = 'clock~clkctrl'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.602 ns) 2.897 ns nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\] 3 REG LCFF_X19_Y11_N21 52 " "Info: 3: + IC(1.080 ns) + CELL(0.602 ns) = 2.897 ns; Loc. = LCFF_X19_Y11_N21; Fanout = 52; REG Node = 'nco1:inst1\|nco1_st:nco1_st_inst\|asj_gar:ux007\|rom_add\[0\]'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.682 ns" { clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } "NODE_NAME" } } { "../../../ip/nco/lib/asj_gar.v" "" { Text "F:/program files/altera/61/ip/nco/lib/asj_gar.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.54 % ) " "Info: Total cell delay = 1.638 ns ( 56.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.259 ns ( 43.46 % ) " "Info: Total interconnect delay = 1.259 ns ( 43.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } { 0.000ns 0.000ns 0.179ns 1.080ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.990 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.990 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 0.000ns 0.179ns 1.028ns } { 0.000ns 1.036ns 0.000ns 0.747ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } { 0.000ns 0.000ns 0.179ns 1.080ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "../../../ip/nco/lib/asj_gar.v" "" { Text "F:/program files/altera/61/ip/nco/lib/asj_gar.v" 29 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" { } { { "db/altsyncram_jq81.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/altsyncram_jq81.tdf" 364 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.741 ns" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "3.741 ns" { nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 3.582ns } { 0.000ns 0.159ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.990 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.990 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { 0.000ns 0.000ns 0.179ns 1.028ns } { 0.000ns 1.036ns 0.000ns 0.747ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clock clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clock clock~combout clock~clkctrl nco1:inst1|nco1_st:nco1_st_inst|asj_gar:ux007|rom_add[0] } { 0.000ns 0.000ns 0.179ns 1.080ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { nco1:inst1|nco1_st:nco1_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_jq81:auto_generated|ram_block1a15~porta_address_reg0 } { } { } "" } } { "db/altsyncram_jq81.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/altsyncram_jq81.tdf" 364 2 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pie_code:inst\|j\[5\] data_in clock 6.412 ns register " "Info: tsu for register \"pie_code:inst\|j\[5\]\" (data pin = \"data_in\", clock pin = \"clock\") is 6.412 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.359 ns + Longest pin register " "Info: + Longest pin to register delay is 9.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.853 ns) 0.853 ns data_in 1 PIN PIN_AA13 9 " "Info: 1: + IC(0.000 ns) + CELL(0.853 ns) = 0.853 ns; Loc. = PIN_AA13; Fanout = 9; PIN Node = 'data_in'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 72 48 216 88 "data_in" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.314 ns) + CELL(0.178 ns) 7.345 ns pie_code:inst\|j\[7\]~858 2 COMB LCCOMB_X32_Y17_N26 1 " "Info: 2: + IC(6.314 ns) + CELL(0.178 ns) = 7.345 ns; Loc. = LCCOMB_X32_Y17_N26; Fanout = 1; COMB Node = 'pie_code:inst\|j\[7\]~858'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.492 ns" { data_in pie_code:inst|j[7]~858 } "NODE_NAME" } } { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.294 ns) + CELL(0.521 ns) 8.160 ns pie_code:inst\|j~859 3 COMB LCCOMB_X32_Y17_N14 6 " "Info: 3: + IC(0.294 ns) + CELL(0.521 ns) = 8.160 ns; Loc. = LCCOMB_X32_Y17_N14; Fanout = 6; COMB Node = 'pie_code:inst\|j~859'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { pie_code:inst|j[7]~858 pie_code:inst|j~859 } "NODE_NAME" } } { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.545 ns) 9.263 ns pie_code:inst\|j~863 4 COMB LCCOMB_X33_Y17_N24 1 " "Info: 4: + IC(0.558 ns) + CELL(0.545 ns) = 9.263 ns; Loc. = LCCOMB_X33_Y17_N24; Fanout = 1; COMB Node = 'pie_code:inst\|j~863'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.103 ns" { pie_code:inst|j~859 pie_code:inst|j~863 } "NODE_NAME" } } { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 9.359 ns pie_code:inst\|j\[5\] 5 REG LCFF_X33_Y17_N25 5 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 9.359 ns; Loc. = LCFF_X33_Y17_N25; Fanout = 5; REG Node = 'pie_code:inst\|j\[5\]'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { pie_code:inst|j~863 pie_code:inst|j[5] } "NODE_NAME" } } { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 23.43 % ) " "Info: Total cell delay = 2.193 ns ( 23.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.166 ns ( 76.57 % ) " "Info: Total interconnect delay = 7.166 ns ( 76.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.359 ns" { data_in pie_code:inst|j[7]~858 pie_code:inst|j~859 pie_code:inst|j~863 pie_code:inst|j[5] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "9.359 ns" { data_in data_in~combout pie_code:inst|j[7]~858 pie_code:inst|j~859 pie_code:inst|j~863 pie_code:inst|j[5] } { 0.000ns 0.000ns 6.314ns 0.294ns 0.558ns 0.000ns } { 0.000ns 0.853ns 0.178ns 0.521ns 0.545ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 2480 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 2480; COMB Node = 'clock~clkctrl'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.092 ns) + CELL(0.602 ns) 2.909 ns pie_code:inst\|j\[5\] 3 REG LCFF_X33_Y17_N25 5 " "Info: 3: + IC(1.092 ns) + CELL(0.602 ns) = 2.909 ns; Loc. = LCFF_X33_Y17_N25; Fanout = 5; REG Node = 'pie_code:inst\|j\[5\]'" { } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.694 ns" { clock~clkctrl pie_code:inst|j[5] } "NODE_NAME" } } { "pie_code.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/pie_code.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.31 % ) " "Info: Total cell delay = 1.638 ns ( 56.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.271 ns ( 43.69 % ) " "Info: Total interconnect delay = 1.271 ns ( 43.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clock clock~clkctrl pie_code:inst|j[5] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clock clock~combout clock~clkctrl pie_code:inst|j[5] } { 0.000ns 0.000ns 0.179ns 1.092ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.359 ns" { data_in pie_code:inst|j[7]~858 pie_code:inst|j~859 pie_code:inst|j~863 pie_code:inst|j[5] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "9.359 ns" { data_in data_in~combout pie_code:inst|j[7]~858 pie_code:inst|j~859 pie_code:inst|j~863 pie_code:inst|j[5] } { 0.000ns 0.000ns 6.314ns 0.294ns 0.558ns 0.000ns } { 0.000ns 0.853ns 0.178ns 0.521ns 0.545ns 0.096ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clock clock~clkctrl pie_code:inst|j[5] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clock clock~combout clock~clkctrl pie_code:inst|j[5] } { 0.000ns 0.000ns 0.179ns 1.092ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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