{ "Info" "ITDB_FULL_TCO_RESULT" "clock mod_out\[11\] ask_modulation:inst10\|Q\[11\] 10.809 ns register " "Info: tco from clock \"clock\" to destination pin \"mod_out\[11\]\" through register \"ask_modulation:inst10\|Q\[11\]\" is 10.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.935 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 2480 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 2480; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.602 ns) 2.935 ns ask_modulation:inst10\|Q\[11\] 3 REG LCFF_X30_Y21_N3 2 " "Info: 3: + IC(1.118 ns) + CELL(0.602 ns) = 2.935 ns; Loc. = LCFF_X30_Y21_N3; Fanout = 2; REG Node = 'ask_modulation:inst10\|Q\[11\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { clock~clkctrl ask_modulation:inst10|Q[11] } "NODE_NAME" } } { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 55.81 % ) " "Info: Total cell delay = 1.638 ns ( 55.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.297 ns ( 44.19 % ) " "Info: Total interconnect delay = 1.297 ns ( 44.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { clock clock~clkctrl ask_modulation:inst10|Q[11] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { clock clock~combout clock~clkctrl ask_modulation:inst10|Q[11] } { 0.000ns 0.000ns 0.179ns 1.118ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.597 ns + Longest register pin " "Info: + Longest register to pin delay is 7.597 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ask_modulation:inst10\|Q\[11\] 1 REG LCFF_X30_Y21_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y21_N3; Fanout = 2; REG Node = 'ask_modulation:inst10\|Q\[11\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { ask_modulation:inst10|Q[11] } "NODE_NAME" } } { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.545 ns) 1.700 ns mmm:inst9\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated\|result_node\[11\]~618 2 COMB LCCOMB_X37_Y21_N30 1 " "Info: 2: + IC(1.155 ns) + CELL(0.545 ns) = 1.700 ns; Loc. = LCCOMB_X37_Y21_N30; Fanout = 1; COMB Node = 'mmm:inst9\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated\|result_node\[11\]~618'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ask_modulation:inst10|Q[11] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 } "NODE_NAME" } } { "db/mux_9oc.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/mux_9oc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.037 ns) + CELL(2.860 ns) 7.597 ns mod_out\[11\] 3 PIN PIN_K25 0 " "Info: 3: + IC(3.037 ns) + CELL(2.860 ns) = 7.597 ns; Loc. = PIN_K25; Fanout = 0; PIN Node = 'mod_out\[11\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.897 ns" { mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 mod_out[11] } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 296 664 840 312 "mod_out\[13..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.405 ns ( 44.82 % ) " "Info: Total cell delay = 3.405 ns ( 44.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.192 ns ( 55.18 % ) " "Info: Total interconnect delay = 4.192 ns ( 55.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.597 ns" { ask_modulation:inst10|Q[11] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 mod_out[11] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.597 ns" { ask_modulation:inst10|Q[11] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 mod_out[11] } { 0.000ns 1.155ns 3.037ns } { 0.000ns 0.545ns 2.860ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { clock clock~clkctrl ask_modulation:inst10|Q[11] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { clock clock~combout clock~clkctrl ask_modulation:inst10|Q[11] } { 0.000ns 0.000ns 0.179ns 1.118ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.597 ns" { ask_modulation:inst10|Q[11] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 mod_out[11] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.597 ns" { ask_modulation:inst10|Q[11] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[11]~618 mod_out[11] } { 0.000ns 1.155ns 3.037ns } { 0.000ns 0.545ns 2.860ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "mod_sel\[1\] mod_out\[5\] 9.957 ns Longest " "Info: Longest tpd from source pin \"mod_sel\[1\]\" to destination pin \"mod_out\[5\]\" is 9.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns mod_sel\[1\] 1 PIN PIN_C13 32 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_C13; Fanout = 32; PIN Node = 'mod_sel\[1\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mod_sel[1] } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 56 48 216 72 "mod_sel\[1..0\]" "" } { 48 418 485 64 "mod_sel\[1..0\]" "" } { 48 216 285 64 "mod_sel\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.516 ns) 3.779 ns mmm:inst9\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated\|result_node\[5\]~624 2 COMB LCCOMB_X29_Y21_N30 1 " "Info: 2: + IC(2.247 ns) + CELL(0.516 ns) = 3.779 ns; Loc. = LCCOMB_X29_Y21_N30; Fanout = 1; COMB Node = 'mmm:inst9\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated\|result_node\[5\]~624'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.763 ns" { mod_sel[1] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[5]~624 } "NODE_NAME" } } { "db/mux_9oc.tdf" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/db/mux_9oc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.338 ns) + CELL(2.840 ns) 9.957 ns mod_out\[5\] 3 PIN PIN_P3 0 " "Info: 3: + IC(3.338 ns) + CELL(2.840 ns) = 9.957 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'mod_out\[5\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.178 ns" { mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[5]~624 mod_out[5] } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 296 664 840 312 "mod_out\[13..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.372 ns ( 43.91 % ) " "Info: Total cell delay = 4.372 ns ( 43.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.585 ns ( 56.09 % ) " "Info: Total interconnect delay = 5.585 ns ( 56.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.957 ns" { mod_sel[1] mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[5]~624 mod_out[5] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "9.957 ns" { mod_sel[1] mod_sel[1]~combout mmm:inst9|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|result_node[5]~624 mod_out[5] } { 0.000ns 0.000ns 2.247ns 3.338ns } { 0.000ns 1.016ns 0.516ns 2.840ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ask_modulation:inst10\|Q\[0\] mod_sel\[1\] clock 0.426 ns register " "Info: th for register \"ask_modulation:inst10\|Q\[0\]\" (data pin = \"mod_sel\[1\]\", clock pin = \"clock\") is 0.426 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.935 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clock~clkctrl 2 COMB CLKCTRL_G3 2480 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 2480; COMB Node = 'clock~clkctrl'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 40 48 216 56 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.602 ns) 2.935 ns ask_modulation:inst10\|Q\[0\] 3 REG LCFF_X31_Y21_N7 2 " "Info: 3: + IC(1.118 ns) + CELL(0.602 ns) = 2.935 ns; Loc. = LCFF_X31_Y21_N7; Fanout = 2; REG Node = 'ask_modulation:inst10\|Q\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { clock~clkctrl ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 55.81 % ) " "Info: Total cell delay = 1.638 ns ( 55.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.297 ns ( 44.19 % ) " "Info: Total interconnect delay = 1.297 ns ( 44.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { clock clock~clkctrl ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { clock clock~combout clock~clkctrl ask_modulation:inst10|Q[0] } { 0.000ns 0.000ns 0.179ns 1.118ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.795 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns mod_sel\[1\] 1 PIN PIN_C13 32 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_C13; Fanout = 32; PIN Node = 'mod_sel\[1\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mod_sel[1] } "NODE_NAME" } } { "ask_mod.bdf" "" { Schematic "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_mod.bdf" { { 56 48 216 72 "mod_sel\[1..0\]" "" } { 48 418 485 64 "mod_sel\[1..0\]" "" } { 48 216 285 64 "mod_sel\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.361 ns) + CELL(0.322 ns) 2.699 ns ask_modulation:inst10\|Q~7288 2 COMB LCCOMB_X31_Y21_N6 1 " "Info: 2: + IC(1.361 ns) + CELL(0.322 ns) = 2.699 ns; Loc. = LCCOMB_X31_Y21_N6; Fanout = 1; COMB Node = 'ask_modulation:inst10\|Q~7288'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.683 ns" { mod_sel[1] ask_modulation:inst10|Q~7288 } "NODE_NAME" } } { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.795 ns ask_modulation:inst10\|Q\[0\] 3 REG LCFF_X31_Y21_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.795 ns; Loc. = LCFF_X31_Y21_N7; Fanout = 2; REG Node = 'ask_modulation:inst10\|Q\[0\]'" {  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { ask_modulation:inst10|Q~7288 ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "ask_modulation.vhd" "" { Text "F:/program files/altera/61/qdesigns/my_work/ask_mod/ask_modulation.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.434 ns ( 51.31 % ) " "Info: Total cell delay = 1.434 ns ( 51.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.361 ns ( 48.69 % ) " "Info: Total interconnect delay = 1.361 ns ( 48.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.795 ns" { mod_sel[1] ask_modulation:inst10|Q~7288 ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.795 ns" { mod_sel[1] mod_sel[1]~combout ask_modulation:inst10|Q~7288 ask_modulation:inst10|Q[0] } { 0.000ns 0.000ns 1.361ns 0.000ns } { 0.000ns 1.016ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { clock clock~clkctrl ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { clock clock~combout clock~clkctrl ask_modulation:inst10|Q[0] } { 0.000ns 0.000ns 0.179ns 1.118ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } } { "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.795 ns" { mod_sel[1] ask_modulation:inst10|Q~7288 ask_modulation:inst10|Q[0] } "NODE_NAME" } } { "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "2.795 ns" { mod_sel[1] mod_sel[1]~combout ask_modulation:inst10|Q~7288 ask_modulation:inst10|Q[0] } { 0.000ns 0.000ns 1.361ns 0.000ns } { 0.000ns 1.016ns 0.322ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}