library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pie_code is
generic(--D : integer := 4;
		code_period : integer := 100);--code_period=1250 means Tari=25us

port(clk : in std_logic;
--	p : integer := 0;
	mod_sel: in std_logic_vector (1 downto 0);
	I : in std_logic;
	Q : out std_logic);
end pie_code;


architecture behave of pie_code is
--signal c : std_logic_vector(D downto 0);
signal j : integer range 0 to code_period*2-1 :=0 ;
--signal k : integer range 0 to code_period-1 :=0 ;
--signal p : integer range 0 to 15 ;
begin
	process(clk)
	begin
		
		if clk'event and clk='1' then
		
			if (mod_sel(1)='0' and mod_sel(0)='1') then--mod_sel[1..0]='01' means PR-ASK Mod
				Q<=I;
			elsif (I='0' and j<code_period/2) then--data '0' transform to Tari
				j<=j+1;
				Q<='1';
			elsif (I='0' and j>=code_period/2) then
				j<=j+1;
				Q<='0';
				if (j=code_period-1) then
					j<=0;
				end if;
			elsif (I='1' and j<code_period*3/2) then--data '1' transfrom
				j<=j+1;
				Q<='1';
			elsif (I='1' and j>=code_period*3/2) then
				j<=j+1;
				Q<='0';
				if (j=code_period*2-1) then
					j<=0;
				end if;	
			end if;
			
		end if;
	end process;
end behave;