LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY timec IS
	PORT(	seca:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			secb:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			mina:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			minb:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			hra:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			hrb:	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			rst:	IN	STD_LOGIC;
			sel:	IN	STD_LOGIC_VECTOR(2 DOWNTO 0);
			q:		OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		 );
END timec;

ARCHITECTURE rtl OF timec IS
BEGIN
	PROCESS(rst,sel,seca,secb,mina,minb,hra,hrb)
	BEGIN
		IF rst='0' THEN
			q<="00000000";
		ELSE
		CASE sel IS
			WHEN "000"=>q<="1"&seca(6 downto 0);
			WHEN "001"=>q<=secb;
			WHEN "010"=>q<="1"&mina(6 downto 0);
			WHEN "011"=>q<=minb;
			WHEN "100"=>q<="1"&hra(6 downto 0);
			WHEN "101"=>q<=hrb;
			WHEN OTHERS=>q<="00000000";
		END CASE;
		END IF;
	END PROCESS;
END rtl;