//顯示所接受正確序列的個(gè)數(shù)
module hex(clk,rst,Y_or_NO,hex0,hex1,ledg);
input clk;
input rst;
input Y_or_NO;
output [6:0] hex0,hex1;
output reg ledg;//燈的控制信號(hào)
reg [3:0] h0,h1;

always @(posedge clk or negedge rst) 
begin	   
	if (!rst)
	begin 
		h0<=4'b0;
		h1<=4'b0;
		ledg<=1'b0;
	end
/*	else if(load)//這是置位的一段程序
	begin 
		h3=(SW[9:6])>9 ? 9:SW[9:6];
		h2=(SW[9:6])>9 ? 9:SW[9:6];
    end
*/
	else if(Y_or_NO)//檢測(cè)到一個(gè)正確的序列，計(jì)數(shù)器加1
	begin
	    ledg<=1'b1;
		if(h0==4'h9)
		begin 
			h0<=4'b0;
			if(h1==4'h9) h1<=4'b0;				
			else h1<=h1+4'b1;
		end
	    else h0<=h0+4'b1;
	end
	else 
	begin 
        ledg<=1'b0;
		h0<=h0;
		h1<=h1;
    end
end
decode4_7 decode0(hex0,h0);
decode4_7 decode1(hex1,h1);
endmodule