--===================================================================--
--
--  www.OpenCores.Org - January 2000
--  This model adheres to the GNU public license  
--
-- Design units   : Target device for PCI Local Bus 33 MHz 32 bits
--                  (BoardLevel Simulation model)
--                  (Entity and architecture)
--
-- File name      : Tg32PCI.vhd
--
-- Purpose        : The Target device is used to simulate a target 
--                  device on the PCI-Bus
--
-- Note           : This model is modelled after the PCI protocol 
--                  as described in Xilinx & Altera AppNotes
--
--                There can be used more than one target devices in a
--                design, every device being identified by the three 
--                base addresses in generic.
--
-- Limitations    : None known
--
-- Errors         : None known
--
-- Library        : PCI_Lib.vhd
--
-- Dependencies   : IEEE.Std_Logic_1164
--
-- Author         : Ovidiu Lupas
--                  olupas@opencores.org
--
-- Simulator    : ModelSim EE version 5.2 on a Windows95 PC
--                ActiveVHDL 3.1 on a Windows95 PC
--===================================================================--
-----------------------------------------------------------------------
-- Entity for Target device in a PCI bus 33 MHZ 32 bit configuration
-----------------------------------------------------------------------
library ieee,work;
  use ieee.Std_Logic_1164.all;
  use work.Simulation.all;
  use work.PCI_Def.all;	
-----------------------------------------------------------------------
-----------------------------------------------------------------------
entity TG32PCI is
    generic (
      devtype : string(1 to 4); -- type of the device (Fast, Medi, Slow)
      tdelay  : Time;   -- delay time parameter when the device will change
                        -- data on AD_Bus (referenced to CLK signal)
      tsetup  : Time;
      thold   : Time;
      bamem   : Std_Logic_Vector(31 downto 0);  -- base address for memory
      baio    : Std_Logic_Vector(31 downto 0);  -- base address for I/O port
      bacfg   : Std_Logic_Vector(31 downto 0)); -- base address for cfg space
    port (
        -- Address, Data and Command buses (37)
        AD_Bus   : inout Std_Logic_Vector (31 downto 0); -- Address and Data Bus
        C_BE_Bus : in    Std_Logic_Vector (3 downto 0);  -- Command Bus
        PAR      : inout Std_Logic;                      --
        -- Interface control signals (6)
        FRAME_N  : in    Std_Logic;
        TRDY_N   : inout Std_Logic;
        IRDY_N   : in    Std_Logic;
        STOP_N   : out   Std_Logic;
        DEVSEL_N : inout Std_Logic;
        IDSEL    : in    Std_Logic;
        -- Error reporting signals (2)
        PERR_N   : inout Std_Logic;
        SERR_N   : inout Std_Logic;
        -- System signals (2)
        CLK      : in    Std_Logic;
        RST_N    : in    Std_Logic);
end TG32PCI; --=================== End of entity ====================--
-----------------------------------------------------------------------
-- Architecture for Target device PCI bus 33MHZ 32 bit configuration
-----------------------------------------------------------------------
architecture Behavior of Target32PCI is
  ---------------------------------------------------------------------
  -- Definition of Memory type,
  ---------------------------------------------------------------------
  type MEMORY is array(0 to 255) of Std_Logic_Vector(31 downto 0);
  ---------------------------------------------------------------------
  -- Local declarations
  ---------------------------------------------------------------------
  shared variable addr      : Std_Logic_Vector (31 downto 0);  -- Address
  shared variable busaddr   : Integer;     -- address present on bus
  shared variable cfgaddr   : Integer;     -- current configuration register address
  shared variable memaddr   : Integer;     -- current memory address
  shared variable ioaddr    : Integer;     -- current I/O port address
  shared variable IOmem     : Memory;      -- IOport registers
  shared variable Cfgmem    : Memory;      -- Configuration registers
  shared variable Mem       : Memory;      -- memory locations
  shared variable trdywaits : Boolean := false; -- wait enable
  shared variable trdy_st,trdy_nr,trdy_loop : Integer := 0;
  ---------------------------------------------------------------------
  -- Signals
  ---------------------------------------------------------------------  
  signal cmd         : Std_Logic_Vector (3 downto 0);   -- Command bus
  signal Busy        : Std_Logic := '0';
  signal IORead      : Std_Logic := '0';
  signal IOWrite     : Std_Logic := '0';
  signal MemRead     : Std_Logic := '0';
  signal MemWrite    : Std_Logic := '0';
  signal WaitWrite   : Std_Logic := '0';
  signal CfgRead     : Std_Logic := '0';
  signal CfgWrite    : Std_Logic := '0';
  signal FrameEv     : Std_Logic := '0';
  signal CmdBusReady : Std_Logic := '0';
  signal TrnArnd     : Std_Logic := '0';
  signal DevAddr     : Std_Logic := '0';
  signal ResFin      : Std_Logic := '0';
  signal Waits       : Std_Logic := '0';
  signal Init        : Std_Logic := '0';
begin--======================== Architecture ========================--
  ---------------------------------------------------------------------
  -- Initialize the memory contents with zeroes
  ---------------------------------------------------------------------
  Initialize : process
  begin
     for i in 0 to 255 loop
         IOmem(i)  := x"00000000";
         Mem(i)    := x"00000000";
         Cfgmem(i) := x"00000000";
     end loop;
     wait;
  end process;
  ---------------------------------------------------------------------
  -- Implements the parity generation and parity checking over the
  -- AD bus and C/BE bus.
  -- Also, generates the PERR_N signal, if the computed parity is not 
  -- equal with PAR signal, when PAR signal is generated by master
  ---------------------------------------------------------------------
  Parity : process(CLK,RST_N)
     variable parbit  : Std_Logic;
     variable lastpar : Std_Logic;
     variable errbit  : Std_Logic;
     variable pargen  : Boolean := false;
     variable errgen  : Boolean := false;
     variable cmdbus  : Std_Logic_Vector(3 downto 0);
     variable addrbus : Std_Logic_Vector(31 downto 0);
  begin
     if (Falling_Edge(RST_N) or RST_N = '0') then
        PAR <= 'Z';
        PERR_N <= 'Z';
     elsif (CLK'Event and CLK = '1') then  -- parity computation on every cycle
         addrbus := AD_Bus;
         cmdbus  := C_BE_Bus;
         lastpar := parbit;
         parbit  := '0';
         if addrbus /= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" then
            for I in 0 to 31 loop
                parbit := parbit xor addrbus(i);
            end loop;
            for I in 0 to 3 loop
                parbit := parbit xor cmdbus(I);
            end loop;
         else
            parbit := 'Z';
         end if;
         if PAR = lastpar then -- PERR computation on every cycle
            errbit := '1';
         elsif PAR /= lastpar then
            errbit := '0';
         elsif PAR = 'Z' then
            errbit := 'H';
         end if;
         if ((IORead = '1' or MemRead = '1' or CfgRead = '1') and DevAddr = '1') then
            pargen := true;
         else
            pargen := false;
         end if;
     elsif (CLK'Event and CLK = '0' and DevAddr = '1') then -- parity generation if necessary
         if errgen = true then
            PERR_N <= errbit;
         else
            PERR_N <= 'H';
         end if;
         if pargen = true then
            PAR <= parbit;
            errgen := false;
         else
            PAR <= 'Z';
            errgen := true;
         end if;
     elsif (CLK'Event and CLK = '0' and DevAddr = '0') then --not the selected device
         PAR    <= 'Z';                            -- by the address
         PERR_N <= 'H';
         SERR_N <= 'Z';
     end if;
  end process;
  ---------------------------------------------------------------------
  -- Implements the command decoding, to receive commands from master
  ---------------------------------------------------------------------
  Decode : process(CLK,FRAME_N,Busy,DevAddr,cmdBusReady,RST_N)
     variable counter : Integer;
     variable devdel  : Boolean := false;
  begin
    if (Falling_Edge(RST_N) or RST_N = '0') then
        DEVSEL_N <= 'Z';
        STOP_N   <= 'Z';
        Busy <= '0';
    elsif (Frame_N'Event and Frame_N = '0') then -- the target device is awakened by 
        FrameEv <= '1';                        -- falling_edge of FRAME signal
        counter := 0;
    elsif (Busy'Event and Busy = '0') then
        IOWrite  <= '0';
        MemWrite <= '0';
        CfgWrite <= '0';
        WaitWrite <= '0';
        IORead   <= '0';
        MemRead  <= '0';
        CfgRead  <= '0';
    elsif (Busy'Event and Busy = '1') then
       if ( IOWrite = '1' or MemWrite = '1' or CfgWrite = '1' or WaitWrite = '1') then
          report "Target device is selected for write operations!"
          severity Note;
          if devtype = "Fast" then
             DEVSEL_N <= '0' after 8 ns;
             Stop_N   <= '1' after 10 ns;
             devdel := false;
          else
             devdel := true;
             counter := 0;
          end if;
       elsif ( IORead = '1' or MemRead = '1' or CfgRead = '1') then
          report "Target device is selected for read operations!"
          severity Note;
          if devtype = "Fast" then
             DEVSEL_N <= '0' after 8 ns;
             Stop_N   <= '1' after 10 ns;
             devdel := false;
          else
             devdel := true;
             counter := 0;
          end if;
       end if;
    elsif (DevAddr'Event and DevAddr = '0') then
       Busy <= '0';