//----------------------------------------------------------------------------
// 
//  Name:  i2c.v   
// 
//  Description: top-level moduel for I2C serial controller
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: techsupport@latticesemi.com
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
Module  i2c
This is the top level module for the multiple I2c Controller. It 
includes the following sub modules:

i2c_wreg.v      contains all the write registers in the design.

i2c_rreg.v      contains all the read registers in the design.

i2c_clk.v       divides the cpu clock into slow speed i2c clock.

i2c_st.v        state machine.
                
i2c_tbuf.v      i2c signal tri-state buffers.

*/

module i2c(     data,               // cpu signals
                addr,
                rst_l,
                clock,
                cs_l,
                ack_l,
                rd_wr_l,
                reg_clk_in,         // clock in  for input regs
                
                reg_clk_out,        // clock out for input regs
                
                scl_pin,            // i2c clock
                sda_pin);           // i2c data
                

//-------------------------------------------------------------------
// microprocessor interface

inout   [7:0]   data;               // cpu data bus
input   [1:0]   addr;               // cpu address bus
input           rst_l;              // async reset
input           clock;              // cpu clock
input           cs_l;               // chip select
input           rd_wr_l;            // read/write
input           reg_clk_in;         // reg write clock in

output          reg_clk_out;        // reg write clock out

output          ack_l;              // acknowledge out to cpu

//-------------------------------------------------------------------
// i2c interface

output          scl_pin;            // i2c clock
inout           sda_pin;            // i2c data
                 
//-------------------------------------------------------------------
// interconnect wires

// cpu interface wires
wire    [7:0]   data;               // cpu data bus
wire    [1:0]   addr;               // cpu address bus
wire            rst_l;              // async reset
wire            clock;              // cpu clock
wire            cs_l;               // chip select
wire            rd_wr_l;            // read/write
wire            reg_clk_in;         // reg write clock in

wire            reg_clk_out;        // reg write clock out
wire            ack_l;              // acknowledge out to cpu

// i2c interface wires

wire            scl_pin;
wire            sda_pin;

// register output wires

wire    [7:0]   wrd_add;            // i2c address
wire            i2c_go;             // i2c start cycle

// read register output wires
                
wire    [7:0]   data_o;             // read data mux out

// clock output wires
wire            scl_tick;           // 5 usec clock tick

// state machine wires

wire            scl_cnt_en;         // scl cntr enable
wire            i2c_rdy;            // read data available
wire            i2c_act;            // i2c cycle active
wire    [7:0]   i2c_rdata;          // i2c read data
wire            ack_err;            // ack error
wire            sda;                // i2c data
wire            scl;                // i2c clock

//-------------------------------------------------------------------
// module instantiations

// write data registers
i2c_wreg U1(    .data(data),
                .addr(addr),
                .rst_l(rst_l),
                .clock(clock),
                .cs_l(cs_l),
                .rd_wr_l(rd_wr_l),
                .reg_clk_in(reg_clk_in),
                .reg_clk_out(reg_clk_out),
                .scl_cnt_en(scl_cnt_en),
                .wrd_add(wrd_add),
                .i2c_go(i2c_go),
                .ack_l(ack_l));

// read data regsiters                
i2c_rreg U2(    .wrd_add(wrd_add),
                .i2c_rdy(i2c_rdy),
                .i2c_act(i2c_act),
                .ack_err(ack_err),
                .i2c_rdata(i2c_rdata),
                .addr(addr),
                .data_o(data_o));

// i2c clock
i2c_clk U3(     .rst_l(rst_l),
                .clock(clock),
                .scl_cnt_en(scl_cnt_en),
                .scl_tick(scl_tick));                

// i2c state machine
i2c_st U4(      .rst_l(rst_l),
                .clock(clock),
                .scl_tick(scl_tick),
                .i2c_go(i2c_go),
                .wrd_add(wrd_add),
                .sda_pin(sda_pin),
                .sda(sda),
                .scl(scl),
                .scl_cnt_en(scl_cnt_en),
                .i2c_rdy(i2c_rdy),
                .i2c_act(i2c_act),
                .i2c_rdata(i2c_rdata),
                .ack_err(ack_err));
                
// i2c tri state buffers                
i2c_tbuf U5(    .data_o(data_o),
                .data(data),
                .cs_l(cs_l),
                .rd_wr_l(rd_wr_l),
                .sda(sda),
                .scl(scl),
                .scl_pin(scl_pin),
                .sda_pin(sda_pin));

endmodule

//------------------------------- E O F --------------------------------------