//------------------------------------------------------------------------------// Title        : LAPS_MANAGEMENT// // File         : SDH_Spending_Bytes_Receiver.v//// Date         : Nov.23, 2007//// AuthorName   : YAN Jing, //// Student No.  : 2007210578 // // Author       : j-yan03@mails.tsinghua.edu.cn// Email        : //------------------------------------------------------------------------------module  laps_management(                         //input                         Clk,                         Reset,                         Teop,                         Tsop,                         Tdata,                         Din,                         //output                         Renb,                         Reop,                         Rsop,                         Tenb,                         Rdata,                         Dout                        );//=========================================================////============	I/O direction  =============================////=========================================================//input        Clk;input        Reset;input        Teop;input        Tsop;input  [7:0] Tdata;input  [7:0] Din;output       Renb;output       Reop;output       Rsop;output       Tenb;output [7:0] Rdata;output [7:0] Dout;//=========================================================////=================	I/O Type  =============================////=========================================================//wire       Renb;wire       Reop;wire       Rsop;wire       Tenb;wire [7:0] Rdata;wire [7:0] Dout;//=========================================================////============	Internal Signals  ==========================////=========================================================//wire [7:0]  Tdata_out;wire [10:0] bytes_data_num;wire        fifo_trans_wrreq;wire        fifo_trans_rdreq;wire        fifo_trans_empty;wire        fifo_trans_full;	wire        fifo_receive_wrreq;wire        fifo_receive_rdreq;wire        fifo_receive_empty;wire        fifo_receive_full;	wire [7:0]  Tdata_to_enframe;wire [7:0]  enframe_data;wire [7:0]  frame_data;wire [10:0] deframe_payload_num;wire [7:0]  data_from_laps;wire [7:0]  data_deframe;wire        deframe_eop;//=========================================================////===========Module Instantiations ========================////=========================================================//data_receive data_receive_inst(                                 .clk(Clk),                               .rst_n(Reset),                               .Tdata(Tdata),                               .Tsop(Tsop),                               .Teop(Teop),                               .Tdata_out(Tdata_out),                               .fifo_trans_wrreq(fifo_trans_wrreq),                               .bytes_data_num(bytes_data_num)                              );fifo_trans fifo_trans_inst(	                        .aclr(~Reset),	                        .clock(Clk),	                        .data(Tdata_out),  	                        .rdreq(fifo_trans_rdreq),	                        .wrreq(fifo_trans_wrreq),	                        .empty(fifo_trans_empty),	                        .full(fifo_trans_full),	                        .q(Tdata_to_enframe)	                        );enframe enframe_inst(                     .clk(Clk),                     .rst_n(Reset),                     .Tsop(Tsop),                     .bytes_data_num(bytes_data_num),                     .Tdata_to_enframe(Tdata_to_enframe),                     .fifo_trans_rdreq(fifo_trans_rdreq),                     .Dout(enframe_data),                     .Tenb(Tenb)                    );scram_encode scram_encode_inst(                                .clk(Clk),                                .rst_n(Reset),                                .enframe_data(enframe_data),                                .scram_data(Dout)                              );scram_decode scram_decode(                           .clk(Clk),                           .rst_n(Reset),                           .scram_data_in(Din),                           .frame_data(frame_data)                          );deframe deframe_inst(                       .clk(Clk),                     .rst_n(Reset),                     .Din(frame_data),                     .bytes_data_num(deframe_payload_num),                     .data_from_laps(data_from_laps),                     .fifo_receive_wrreq(fifo_receive_wrreq),                     .deframe_eop(deframe_eop)                                       );                    fifo_receive fifo_receive_inst(	                        .aclr(~Reset),	                        .clock(Clk),	                        .data(data_from_laps),  	                        .rdreq(fifo_receive_rdreq),	                        .wrreq(fifo_receive_wrreq),	                        .empty(fifo_receive_empty),	                        .full(fifo_receive_full),	                        .q(data_deframe)	                        );	                        data_trans data_trans_inst(                           .clk(Clk),                           .rst_n(Reset),                           .data_deframe(data_deframe),                           .deframe_eop(deframe_eop),                           .bytes_data_num(deframe_payload_num),                           .fifo_receive_empty(fifo_receive_empty),                           .Rdata(Rdata),                           .Rsop(Rsop),                           .Reop(Reop),                           .Renb(Renb),                           .fifo_receive_rdreq(fifo_receive_rdreq)                          );endmodule