-- Vhdl test bench created from schematic swepfre.sch - Fri Oct 05 10:44:07 2007
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY swepfre_swepfre_sch_tb IS
END swepfre_swepfre_sch_tb;
ARCHITECTURE behavioral OF swepfre_swepfre_sch_tb IS 

   COMPONENT swepfre
   PORT( clk40	:	IN	STD_LOGIC; 
          sin_out	:	OUT	STD_LOGIC_VECTOR (5 DOWNTO 0));
   END COMPONENT;

   SIGNAL clk40	:	STD_LOGIC:='1';
   SIGNAL sin_out	:	STD_LOGIC_VECTOR (5 DOWNTO 0);

BEGIN

   UUT: swepfre PORT MAP(
		clk40 => clk40, 
		sin_out => sin_out
   );
				clk40<=not clk40 after 0.0125us;
-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;