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-- Company: 
-- Engineer:
--
-- Create Date:    16:56:14 09/30/07
-- Design Name:    
-- Module Name:    swep_fre - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity swep_fre is
    Port ( clk : in std_logic;
           rst : in std_logic;
           accu_out : out std_logic_vector(31 downto 0));
end swep_fre;

architecture Behavioral of swep_fre is


signal fre_begin: std_logic_vector(31 downto 0):="00001010101010101010101010101010";	 --5M
signal fre_word:std_logic_vector(31 downto 0):=(others=>'0'); -- 頻率控制字
signal fre_step: std_logic_vector(31 downto 0):="00000000011100011100011100011100"; 	  --	掃頻間隔25/120=
signal cnt:integer range 0 to 1500:=0;


signal mid_result:std_logic_vector(31 downto 0):=(others=>'0');  
 
  begin
     process(clk,rst)
      begin
		 if rst='1' then
		 fre_word<=fre_begin;
		
       else
		   if clk'event and clk='1' then 
			       if cnt<120 then --控制掃頻信號周期	1us+11us
		          cnt<=cnt+1;
		          fre_word<=fre_begin+fre_step;
		          mid_result<=mid_result+fre_word;
					 elsif cnt>119 then
					   if cnt=1440 then
						cnt<=0;
						fre_word<=fre_begin;
						else cnt<=cnt+1;
						     mid_result<=(others=>'0');  
						end if;
                end if;
	      else
	      mid_result<=mid_result;	
         end if;
      end if;
     end process; 
			
		
			

        	accu_out<=mid_result;

	  
		


end Behavioral;