Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 2.50 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 2.50 s | Elapsed : 0.00 / 1.00 s --> Reading design: swepfre.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "swepfre.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "swepfre"Output Format                      : NGCTarget Device                      : xc4vsx55-10-ff1148---- Source OptionsTop Module Name                    : swepfreAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 32Number of Regional Clock Buffers   : DefaultRegister Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : swepfre.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : Nouse_dsp48                          : autoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Autouse_sync_set                       : Autouse_sync_reset                     : Autoenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/rfid/rfid_re/sincos.vhd" in Library work.Compiling vhdl file "D:/rfid/rfid_re/dcm_160.vhd" in Library work.Entity <dcm_160> compiled.Entity <dcm_160> (Architecture <behavioral>) compiled.Compiling vhdl file "D:/rfid/rfid_re/rst_gen.vhd" in Library work.Architecture behavioral of Entity rst_gen is up to date.Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.Architecture behavioral of Entity swep_fre is up to date.Compiling vhdl file "D:/rfid/rfid_re/trunction.vhd" in Library work.Architecture behavioral of Entity trunction is up to date.Compiling vhdl file "D:/rfid/rfid_re/findsin.vhd" in Library work.Architecture behavioral of Entity findsin is up to date.Compiling vhdl file "D:/rfid/rfid_re/swepfre.vhf" in Library work.Entity <swepfre> compiled.Entity <swepfre> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <swepfre> (Architecture <behavioral>).    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <XLXI_9> in unit <swepfre>.    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <XLXI_9> in unit <swepfre>.WARNING:Xst:753 - "D:/rfid/rfid_re/swepfre.vhf" line 100: Unconnected output port 'CLK0_OUT' of component 'dcm_160'.Entity <swepfre> analyzed. Unit <swepfre> generated.Analyzing Entity <dcm_160> (Architecture <behavioral>).WARNING:Xst:766 - "D:/rfid/rfid_re/dcm_160.vhd" line 99: Generating a Black Box for component <BUFG>.WARNING:Xst:766 - "D:/rfid/rfid_re/dcm_160.vhd" line 103: Generating a Black Box for component <BUFG>.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLK90' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLK180' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLK270' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLKDV' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLK2X' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLK2X180' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'CLKFX180' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'DRDY' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'DO' of component 'DCM_ADV'.WARNING:Xst:753 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Unconnected output port 'PSDONE' of component 'DCM_ADV'.WARNING:Xst:766 - "D:/rfid/rfid_re/dcm_160.vhd" line 107: Generating a Black Box for component <DCM_ADV>.Entity <dcm_160> analyzed. Unit <dcm_160> generated.Analyzing Entity <rst_gen> (Architecture <behavioral>).Entity <rst_gen> analyzed. Unit <rst_gen> generated.Analyzing Entity <swep_fre> (Architecture <behavioral>).WARNING:Xst:819 - "D:/rfid/rfid_re/swep_fre.vhd" line 48: The following signals are missing in the process sensitivity list:   fre_begin.Entity <swep_fre> analyzed. Unit <swep_fre> generated.Analyzing Entity <trunction> (Architecture <behavioral>).Entity <trunction> analyzed. Unit <trunction> generated.Analyzing Entity <findsin> (Architecture <behavioral>).Entity <findsin> analyzed. Unit <findsin> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <findsin>.    Related source file is "D:/rfid/rfid_re/findsin.vhd".    Found 256x6-bit ROM for signal <$n0001> created at line 46.    Found 6-bit register for signal <sinout>.    Summary:	inferred   1 ROM(s).	inferred   6 D-type flip-flop(s).Unit <findsin> synthesized.Synthesizing Unit <trunction>.    Related source file is "D:/rfid/rfid_re/trunction.vhd".WARNING:Xst:647 - Input <phaseaddress<23:0>> is never used.    Found 8-bit register for signal <addresscutted>.    Summary:	inferred   8 D-type flip-flop(s).Unit <trunction> synthesized.Synthesizing Unit <swep_fre>.    Related source file is "D:/rfid/rfid_re/swep_fre.vhd".WARNING:Xst:653 - Signal <fre_begin> is used but never assigned. Tied to value 00001010101010101010101010101010.WARNING:Xst:653 - Signal <fre_step> is used but never assigned. Tied to value 00000000011100011100011100011100.    Found 32-bit 4-to-1 multiplexer for signal <$n0004>.    Found 32-bit adder for signal <$n0007> created at line 57.    Found 32-bit adder for signal <$n0008> created at line 58.    Found 11-bit comparator less for signal <$n0009> created at line 55.    Found 11-bit up counter for signal <cnt>.    Found 32-bit register for signal <fre_word>.    Found 32-bit register for signal <mid_result>.    Summary:	inferred   1 Counter(s).	inferred  32 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred   1 Comparator(s).	inferred  32 Multiplexer(s).Unit <swep_fre> synthesized.Synthesizing Unit <rst_gen>.    Related source file is "D:/rfid/rfid_re/rst_gen.vhd".    Found 1-bit register for signal <rst>.    Found 5-bit up counter for signal <count>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <rst_gen> synthesized.Synthesizing Unit <dcm_160>.    Related source file is "D:/rfid/rfid_re/dcm_160.vhd".Unit <dcm_160> synthesized.Synthesizing Unit <swepfre>.    Related source file is "D:/rfid/rfid_re/swepfre.vhf".Unit <swepfre> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...INFO:Xst:1647 - Data output of ROM <Mrom__n0001> in block <findsin> is tied to register <sinout> in block <findsin>.INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.MAC inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...DSP optimizations ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Block RAMs                       : 1 256x6-bit single-port block RAM   : 1# Adders/Subtractors               : 2 32-bit adder                      : 2# Counters                         : 2 11-bit up counter                 : 1 5-bit up counter                  : 1# Registers                        : 4