1-bit register                    : 1 32-bit register                   : 2 8-bit register                    : 1# Comparators                      : 1 11-bit comparator less            : 1# Multiplexers                     : 1 32-bit 4-to-1 multiplexer         : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1426 - The value init of the FF/Latch rst hinder the constant cleaning in the block rst_gen.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_1 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_7 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_13 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_19 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_25 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch fre_word_27 hinder the constant cleaning in the block swep_fre.   You should achieve better results by setting this init to 1.WARNING:Xst:1293 - FF/Latch  <fre_word_31> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_30> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_0> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_4> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_10> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_16> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_22> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_26> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_28> has a constant value of 0 in block <swep_fre>.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <fre_word_29> has a constant value of 0 in block <swep_fre>.Register <fre_word_19> equivalent to <fre_word_1> has been removedRegister <fre_word_25> equivalent to <fre_word_1> has been removedRegister <fre_word_13> equivalent to <fre_word_1> has been removedRegister <fre_word_7> equivalent to <fre_word_1> has been removedRegister <fre_word_27> equivalent to <fre_word_1> has been removedRegister <fre_word_6> equivalent to <fre_word_2> has been removedRegister <fre_word_8> equivalent to <fre_word_2> has been removedRegister <fre_word_24> equivalent to <fre_word_2> has been removedRegister <fre_word_20> equivalent to <fre_word_2> has been removedRegister <fre_word_18> equivalent to <fre_word_2> has been removedRegister <fre_word_14> equivalent to <fre_word_2> has been removedRegister <fre_word_12> equivalent to <fre_word_2> has been removedRegister <fre_word_5> equivalent to <fre_word_3> has been removedRegister <fre_word_15> equivalent to <fre_word_3> has been removedRegister <fre_word_23> equivalent to <fre_word_3> has been removedRegister <fre_word_21> equivalent to <fre_word_3> has been removedRegister <fre_word_17> equivalent to <fre_word_3> has been removedRegister <fre_word_11> equivalent to <fre_word_3> has been removedRegister <fre_word_9> equivalent to <fre_word_3> has been removedOptimizing unit <swepfre> ...Optimizing unit <rst_gen> ...Optimizing unit <swep_fre> ...Loading device for application Rf_Device from file '4vsx55.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block swepfre, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : swepfre.ngrTop Level Output File Name         : swepfreOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 8Macro Statistics :# RAM                              : 1#      256x6-bit single-port block RAM: 1# Registers                        : 13#      1-bit register              : 11#      32-bit register             : 1#      8-bit register              : 1# Counters                         : 1#      11-bit up counter           : 1# Multiplexers                     : 1#      32-bit 4-to-1 multiplexer   : 1# Adders/Subtractors               : 2#      32-bit adder                : 2# Comparators                      : 1#      11-bit comparator less      : 1Cell Usage :# BELS                             : 187#      GND                         : 1#      INV                         : 4#      LUT1                        : 2#      LUT1_L                      : 9#      LUT2                        : 9#      LUT2_D                      : 1#      LUT2_L                      : 56#      LUT3                        : 1#      LUT3_L                      : 10#      LUT4                        : 7#      LUT4_D                      : 1#      LUT4_L                      : 1#      MUXCY                       : 42#      VCC                         : 1#      XORCY                       : 42# FlipFlops/Latches                : 60#      FD                          : 8#      FDCPE                       : 3#      FDE                         : 44#      FDR                         : 3#      FDS                         : 2# RAMS                             : 1#      RAMB16                      : 1# Clock Buffers                    : 2#      BUFG                        : 2# IO Buffers                       : 8#      IBUFG                       : 1#      OBUF                        : 7# DCMs                             : 1#      DCM_ADV                     : 1=========================================================================Device utilization summary:---------------------------Selected Device : 4vsx55ff1148-10  Number of Slices:                      53  out of  24576     0%   Number of Slice Flip Flops:            60  out of  49152     0%   Number of 4 input LUTs:                97  out of  49152     0%   Number of bonded IOBs:                  8  out of    642     1%   Number of FIFO16/RAMB16s:               1  out of    320     0%      Number used as RAMB16s:              1 Number of GCLKs:                        2  out of     32     6%   Number of DCM_ADVs:                     1  out of      8    12%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+---------------------------+-------+Clock Signal                       | Clock buffer(FF name)     | Load  |-----------------------------------+---------------------------+-------+clk40                              | IBUFG                     | 6     |clk40                              | XLXI_10/DCM_ADV_INST:CLKFX| 55    |-----------------------------------+---------------------------+-------+Timing Summary:---------------Speed Grade: -10   Minimum period: 13.864ns (Maximum Frequency: 72.130MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 5.723ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk40'  Clock period: 13.864ns (frequency: 72.130MHz)  Total number of paths / destination ports: 2870 / 107-------------------------------------------------------------------------Delay:               4.621ns (Levels of Logic = 13)  Source:            XLXI_86/cnt_0 (FF)  Destination:       XLXI_86/cnt_10 (FF)  Source Clock:      clk40 rising 3.0X  Destination Clock: clk40 rising 3.0X  Data Path: XLXI_86/cnt_0 to XLXI_86/cnt_10                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDE:C->Q              2   0.360   0.783  XLXI_86/cnt_0 (XLXI_86/cnt_0)     LUT4:I0->O            1   0.195   0.712  XLXI_86/_n000511 (CHOICE20)     LUT4_D:I1->O         14   0.195   0.832  XLXI_86/_n000544 (XLXI_86/_n0005)     LUT3_L:I2->LO         1   0.195   0.000  XLXI_86/cnt_inst_lut3_11 (XLXI_86/cnt_inst_lut3_1)     MUXCY:S->O            1   0.366   0.000  XLXI_86/cnt_inst_cy_2 (XLXI_86/cnt_inst_cy_2)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_3 (XLXI_86/cnt_inst_cy_3)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_4 (XLXI_86/cnt_inst_cy_4)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_5 (XLXI_86/cnt_inst_cy_5)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_6 (XLXI_86/cnt_inst_cy_6)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_7 (XLXI_86/cnt_inst_cy_7)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_8 (XLXI_86/cnt_inst_cy_8)     MUXCY:CI->O           1   0.044   0.000  XLXI_86/cnt_inst_cy_9 (XLXI_86/cnt_inst_cy_9)     MUXCY:CI->O           0   0.044   0.000  XLXI_86/cnt_inst_cy_10 (XLXI_86/cnt_inst_cy_10)     XORCY:CI->O           1   0.360   0.000  XLXI_86/cnt_inst_sum_10 (XLXI_86/cnt_inst_sum_10)     FDE:D                     0.268          XLXI_86/cnt_10    ----------------------------------------    Total                      4.621ns (2.295ns logic, 2.326ns route)                                       (49.7% logic, 50.3% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk40'  Total number of paths / destination ports: 6 / 6-------------------------------------------------------------------------Offset:              5.723ns (Levels of Logic = 1)  Source:            XLXI_90/Mrom__n00011_inst_ramb_0 (RAM)  Destination:       sin_out<5> (PAD)  Source Clock:      clk40 rising 3.0X  Data Path: XLXI_90/Mrom__n00011_inst_ramb_0 to sin_out<5>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     RAMB16:CLKA->DOA5     1   2.100   0.534  XLXI_90/Mrom__n00011_inst_ramb_0 (sin_out_5_OBUF)     OBUF:I->O                 3.089          sin_out_5_OBUF (sin_out<5>)    ----------------------------------------    Total                      5.723ns (5.189ns logic, 0.534ns route)                                       (90.7% logic, 9.3% route)=========================================================================CPU : 23.06 / 25.80 s | Elapsed : 23.00 / 24.00 s --> Total memory usage is 240560 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :   35 (   0 filtered)Number of infos    :    2 (   0 filtered)