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-- Company: 
-- Engineer:
--
-- Create Date:    19:38:27 09/30/07
-- Design Name:    
-- Module Name:    trunction - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.sincos.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity trunction is
		Port ( clk: in std_logic;
           phaseaddress : in std_logic_vector(31 downto 0);          
           addresscutted : out std_logic_vector(7 downto 0));
end trunction;

architecture Behavioral of trunction is

begin
   process(clk)
   begin     
       if clk'event and clk='1' then
           addresscutted <= phaseaddress(31 downto 24);
	  end if;
   end process;

end Behavioral;