?? fulladder_4.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FullAdder_4 IS
PORT(dataA,dataB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carryin:IN STD_LOGIC;
sum:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carryout:OUT STD_LOGIC);
END ENTITY FullAdder_4;
ARCHITECTURE dataflow OF FullAdder_4 IS
COMPONENT FullAdder
PORT(dataA:IN STD_LOGIC;
dataB:IN STD_LOGIC;
carryin:IN STD_LOGIC;
sum:OUT STD_LOGIC;
carryout:OUT STD_LOGIC);
END COMPONENT;
SIGNAL carry1,carry2,carry3:STD_LOGIC;
BEGIN
u1:FullAdder PORT MAP (dataA(0),dataB(0),carryin,sum(0),carry1);
u2:FullAdder PORT MAP (dataA(1),dataB(1),carry1,sum(1),carry2);
u3:FullAdder PORT MAP (dataA(2),dataB(2),carry2,sum(2),carry3);
u4:FullAdder PORT MAP (dataA(3),dataB(3),carry3,sum(3),carryout);
END ARCHITECTURE dataflow;
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