N1_q_b[6]_PORT_A_data_in = VCC;
N1_q_b[6]_PORT_A_data_in_reg = DFFE(N1_q_b[6]_PORT_A_data_in, N1_q_b[6]_clock_0, , , );
N1_q_b[6]_PORT_B_data_in = P1_ram_rom_data_reg[6];
N1_q_b[6]_PORT_B_data_in_reg = DFFE(N1_q_b[6]_PORT_B_data_in, N1_q_b[6]_clock_1, , , );
N1_q_b[6]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[6]_PORT_A_address_reg = DFFE(N1_q_b[6]_PORT_A_address, N1_q_b[6]_clock_0, , , );
N1_q_b[6]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[6]_PORT_B_address_reg = DFFE(N1_q_b[6]_PORT_B_address, N1_q_b[6]_clock_1, , , );
N1_q_b[6]_PORT_A_write_enable = GND;
N1_q_b[6]_PORT_A_write_enable_reg = DFFE(N1_q_b[6]_PORT_A_write_enable, N1_q_b[6]_clock_0, , , );
N1_q_b[6]_PORT_B_write_enable = P1L92;
N1_q_b[6]_PORT_B_write_enable_reg = DFFE(N1_q_b[6]_PORT_B_write_enable, N1_q_b[6]_clock_1, , , );
N1_q_b[6]_clock_0 = clk;
N1_q_b[6]_clock_1 = A1L5;
N1_q_b[6]_PORT_B_data_out = MEMORY(N1_q_b[6]_PORT_A_data_in_reg, N1_q_b[6]_PORT_B_data_in_reg, N1_q_b[6]_PORT_A_address_reg, N1_q_b[6]_PORT_B_address_reg, N1_q_b[6]_PORT_A_write_enable_reg, N1_q_b[6]_PORT_B_write_enable_reg, , , N1_q_b[6]_clock_0, N1_q_b[6]_clock_1, , , , );
N1_q_b[6] = N1_q_b[6]_PORT_B_data_out[0];


--V1_q_a[6] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[6]_PORT_A_data_in = VCC;
V1_q_a[6]_PORT_A_data_in_reg = DFFE(V1_q_a[6]_PORT_A_data_in, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_data_in = P2_ram_rom_data_reg[6];
V1_q_a[6]_PORT_B_data_in_reg = DFFE(V1_q_a[6]_PORT_B_data_in, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_a[6]_PORT_A_address_reg = DFFE(V1_q_a[6]_PORT_A_address, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_a[6]_PORT_B_address_reg = DFFE(V1_q_a[6]_PORT_B_address, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_PORT_A_write_enable = GND;
V1_q_a[6]_PORT_A_write_enable_reg = DFFE(V1_q_a[6]_PORT_A_write_enable, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_write_enable = P2L92;
V1_q_a[6]_PORT_B_write_enable_reg = DFFE(V1_q_a[6]_PORT_B_write_enable, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_clock_0 = clk;
V1_q_a[6]_clock_1 = A1L5;
V1_q_a[6]_PORT_A_data_out = MEMORY(V1_q_a[6]_PORT_A_data_in_reg, V1_q_a[6]_PORT_B_data_in_reg, V1_q_a[6]_PORT_A_address_reg, V1_q_a[6]_PORT_B_address_reg, V1_q_a[6]_PORT_A_write_enable_reg, V1_q_a[6]_PORT_B_write_enable_reg, , , V1_q_a[6]_clock_0, V1_q_a[6]_clock_1, , , , );
V1_q_a[6] = V1_q_a[6]_PORT_A_data_out[0];

--V1_q_b[6] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_b[6]
V1_q_b[6]_PORT_A_data_in = VCC;
V1_q_b[6]_PORT_A_data_in_reg = DFFE(V1_q_b[6]_PORT_A_data_in, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_data_in = P2_ram_rom_data_reg[6];
V1_q_b[6]_PORT_B_data_in_reg = DFFE(V1_q_b[6]_PORT_B_data_in, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_b[6]_PORT_A_address_reg = DFFE(V1_q_b[6]_PORT_A_address, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_b[6]_PORT_B_address_reg = DFFE(V1_q_b[6]_PORT_B_address, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_write_enable = GND;
V1_q_b[6]_PORT_A_write_enable_reg = DFFE(V1_q_b[6]_PORT_A_write_enable, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_write_enable = P2L92;
V1_q_b[6]_PORT_B_write_enable_reg = DFFE(V1_q_b[6]_PORT_B_write_enable, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_clock_0 = clk;
V1_q_b[6]_clock_1 = A1L5;
V1_q_b[6]_PORT_B_data_out = MEMORY(V1_q_b[6]_PORT_A_data_in_reg, V1_q_b[6]_PORT_B_data_in_reg, V1_q_b[6]_PORT_A_address_reg, V1_q_b[6]_PORT_B_address_reg, V1_q_b[6]_PORT_A_write_enable_reg, V1_q_b[6]_PORT_B_write_enable_reg, , , V1_q_b[6]_clock_0, V1_q_b[6]_clock_1, , , , );
V1_q_b[6] = V1_q_b[6]_PORT_B_data_out[0];


--E1L91 is MUX41A:inst3|DATAOUT[6]~824
--operation mode is normal

E1L91 = n0 & (V1_q_a[6] # n1) # !n0 & !n1 & E1L12;


--E1L12 is MUX41A:inst3|DATAOUT[6]~839
--operation mode is normal

E1L12 = LCELL(E1L91 & (Y1_q_a[6] # !n1) # !E1L91 & N1_q_a[6] & n1);


--Y1_q_a[5] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
Y1_q_a[5]_PORT_A_data_in = VCC;
Y1_q_a[5]_PORT_A_data_in_reg = DFFE(Y1_q_a[5]_PORT_A_data_in, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5]_PORT_B_data_in = P3_ram_rom_data_reg[5];
Y1_q_a[5]_PORT_B_data_in_reg = DFFE(Y1_q_a[5]_PORT_B_data_in, Y1_q_a[5]_clock_1, , , );
Y1_q_a[5]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[5]_PORT_A_address_reg = DFFE(Y1_q_a[5]_PORT_A_address, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[5]_PORT_B_address_reg = DFFE(Y1_q_a[5]_PORT_B_address, Y1_q_a[5]_clock_1, , , );
Y1_q_a[5]_PORT_A_write_enable = GND;
Y1_q_a[5]_PORT_A_write_enable_reg = DFFE(Y1_q_a[5]_PORT_A_write_enable, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5]_PORT_B_write_enable = P3L92;
Y1_q_a[5]_PORT_B_write_enable_reg = DFFE(Y1_q_a[5]_PORT_B_write_enable, Y1_q_a[5]_clock_1, , , );
Y1_q_a[5]_clock_0 = clk;
Y1_q_a[5]_clock_1 = A1L5;
Y1_q_a[5]_PORT_A_data_out = MEMORY(Y1_q_a[5]_PORT_A_data_in_reg, Y1_q_a[5]_PORT_B_data_in_reg, Y1_q_a[5]_PORT_A_address_reg, Y1_q_a[5]_PORT_B_address_reg, Y1_q_a[5]_PORT_A_write_enable_reg, Y1_q_a[5]_PORT_B_write_enable_reg, , , Y1_q_a[5]_clock_0, Y1_q_a[5]_clock_1, , , , );
Y1_q_a[5] = Y1_q_a[5]_PORT_A_data_out[0];

--Y1_q_b[5] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[5]
Y1_q_b[5]_PORT_A_data_in = VCC;
Y1_q_b[5]_PORT_A_data_in_reg = DFFE(Y1_q_b[5]_PORT_A_data_in, Y1_q_b[5]_clock_0, , , );
Y1_q_b[5]_PORT_B_data_in = P3_ram_rom_data_reg[5];
Y1_q_b[5]_PORT_B_data_in_reg = DFFE(Y1_q_b[5]_PORT_B_data_in, Y1_q_b[5]_clock_1, , , );
Y1_q_b[5]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[5]_PORT_A_address_reg = DFFE(Y1_q_b[5]_PORT_A_address, Y1_q_b[5]_clock_0, , , );
Y1_q_b[5]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[5]_PORT_B_address_reg = DFFE(Y1_q_b[5]_PORT_B_address, Y1_q_b[5]_clock_1, , , );
Y1_q_b[5]_PORT_A_write_enable = GND;
Y1_q_b[5]_PORT_A_write_enable_reg = DFFE(Y1_q_b[5]_PORT_A_write_enable, Y1_q_b[5]_clock_0, , , );
Y1_q_b[5]_PORT_B_write_enable = P3L92;
Y1_q_b[5]_PORT_B_write_enable_reg = DFFE(Y1_q_b[5]_PORT_B_write_enable, Y1_q_b[5]_clock_1, , , );
Y1_q_b[5]_clock_0 = clk;
Y1_q_b[5]_clock_1 = A1L5;
Y1_q_b[5]_PORT_B_data_out = MEMORY(Y1_q_b[5]_PORT_A_data_in_reg, Y1_q_b[5]_PORT_B_data_in_reg, Y1_q_b[5]_PORT_A_address_reg, Y1_q_b[5]_PORT_B_address_reg, Y1_q_b[5]_PORT_A_write_enable_reg, Y1_q_b[5]_PORT_B_write_enable_reg, , , Y1_q_b[5]_clock_0, Y1_q_b[5]_clock_1, , , , );
Y1_q_b[5] = Y1_q_b[5]_PORT_B_data_out[0];


--N1_q_a[5] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
N1_q_a[5]_PORT_A_data_in = VCC;
N1_q_a[5]_PORT_A_data_in_reg = DFFE(N1_q_a[5]_PORT_A_data_in, N1_q_a[5]_clock_0, , , );
N1_q_a[5]_PORT_B_data_in = P1_ram_rom_data_reg[5];
N1_q_a[5]_PORT_B_data_in_reg = DFFE(N1_q_a[5]_PORT_B_data_in, N1_q_a[5]_clock_1, , , );
N1_q_a[5]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_a[5]_PORT_A_address_reg = DFFE(N1_q_a[5]_PORT_A_address, N1_q_a[5]_clock_0, , , );
N1_q_a[5]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_a[5]_PORT_B_address_reg = DFFE(N1_q_a[5]_PORT_B_address, N1_q_a[5]_clock_1, , , );
N1_q_a[5]_PORT_A_write_enable = GND;
N1_q_a[5]_PORT_A_write_enable_reg = DFFE(N1_q_a[5]_PORT_A_write_enable, N1_q_a[5]_clock_0, , , );
N1_q_a[5]_PORT_B_write_enable = P1L92;
N1_q_a[5]_PORT_B_write_enable_reg = DFFE(N1_q_a[5]_PORT_B_write_enable, N1_q_a[5]_clock_1, , , );
N1_q_a[5]_clock_0 = clk;
N1_q_a[5]_clock_1 = A1L5;
N1_q_a[5]_PORT_A_data_out = MEMORY(N1_q_a[5]_PORT_A_data_in_reg, N1_q_a[5]_PORT_B_data_in_reg, N1_q_a[5]_PORT_A_address_reg, N1_q_a[5]_PORT_B_address_reg, N1_q_a[5]_PORT_A_write_enable_reg, N1_q_a[5]_PORT_B_write_enable_reg, , , N1_q_a[5]_clock_0, N1_q_a[5]_clock_1, , , , );
N1_q_a[5] = N1_q_a[5]_PORT_A_data_out[0];

--N1_q_b[5] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[5]
N1_q_b[5]_PORT_A_data_in = VCC;
N1_q_b[5]_PORT_A_data_in_reg = DFFE(N1_q_b[5]_PORT_A_data_in, N1_q_b[5]_clock_0, , , );
N1_q_b[5]_PORT_B_data_in = P1_ram_rom_data_reg[5];
N1_q_b[5]_PORT_B_data_in_reg = DFFE(N1_q_b[5]_PORT_B_data_in, N1_q_b[5]_clock_1, , , );
N1_q_b[5]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[5]_PORT_A_address_reg = DFFE(N1_q_b[5]_PORT_A_address, N1_q_b[5]_clock_0, , , );
N1_q_b[5]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[5]_PORT_B_address_reg = DFFE(N1_q_b[5]_PORT_B_address, N1_q_b[5]_clock_1, , , );
N1_q_b[5]_PORT_A_write_enable = GND;
N1_q_b[5]_PORT_A_write_enable_reg = DFFE(N1_q_b[5]_PORT_A_write_enable, N1_q_b[5]_clock_0, , , );
N1_q_b[5]_PORT_B_write_enable = P1L92;
N1_q_b[5]_PORT_B_write_enable_reg = DFFE(N1_q_b[5]_PORT_B_write_enable, N1_q_b[5]_clock_1, , , );
N1_q_b[5]_clock_0 = clk;
N1_q_b[5]_clock_1 = A1L5;
N1_q_b[5]_PORT_B_data_out = MEMORY(N1_q_b[5]_PORT_A_data_in_reg, N1_q_b[5]_PORT_B_data_in_reg, N1_q_b[5]_PORT_A_address_reg, N1_q_b[5]_PORT_B_address_reg, N1_q_b[5]_PORT_A_write_enable_reg, N1_q_b[5]_PORT_B_write_enable_reg, , , N1_q_b[5]_clock_0, N1_q_b[5]_clock_1, , , , );
N1_q_b[5] = N1_q_b[5]_PORT_B_data_out[0];


--V1_q_a[5] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[5]_PORT_A_data_in = VCC;
V1_q_a[5]_PORT_A_data_in_reg = DFFE(V1_q_a[5]_PORT_A_data_in, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_data_in = P2_ram_rom_data_reg[5];
V1_q_a[5]_PORT_B_data_in_reg = DFFE(V1_q_a[5]_PORT_B_data_in, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_a[5]_PORT_A_address_reg = DFFE(V1_q_a[5]_PORT_A_address, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_a[5]_PORT_B_address_reg = DFFE(V1_q_a[5]_PORT_B_address, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_PORT_A_write_enable = GND;
V1_q_a[5]_PORT_A_write_enable_reg = DFFE(V1_q_a[5]_PORT_A_write_enable, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_write_enable = P2L92;
V1_q_a[5]_PORT_B_write_enable_reg = DFFE(V1_q_a[5]_PORT_B_write_enable, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_clock_0 = clk;
V1_q_a[5]_clock_1 = A1L5;
V1_q_a[5]_PORT_A_data_out = MEMORY(V1_q_a[5]_PORT_A_data_in_reg, V1_q_a[5]_PORT_B_data_in_reg, V1_q_a[5]_PORT_A_address_reg, V1_q_a[5]_PORT_B_address_reg, V1_q_a[5]_PORT_A_write_enable_reg, V1_q_a[5]_PORT_B_write_enable_reg, , , V1_q_a[5]_clock_0, V1_q_a[5]_clock_1, , , , );
V1_q_a[5] = V1_q_a[5]_PORT_A_data_out[0];

--V1_q_b[5] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_b[5]
V1_q_b[5]_PORT_A_data_in = VCC;
V1_q_b[5]_PORT_A_data_in_reg = DFFE(V1_q_b[5]_PORT_A_data_in, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_data_in = P2_ram_rom_data_reg[5];
V1_q_b[5]_PORT_B_data_in_reg = DFFE(V1_q_b[5]_PORT_B_data_in, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_b[5]_PORT_A_address_reg = DFFE(V1_q_b[5]_PORT_A_address, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_b[5]_PORT_B_address_reg = DFFE(V1_q_b[5]_PORT_B_address, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_PORT_A_write_enable = GND;
V1_q_b[5]_PORT_A_write_enable_reg = DFFE(V1_q_b[5]_PORT_A_write_enable, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_write_enable = P2L92;
V1_q_b[5]_PORT_B_write_enable_reg = DFFE(V1_q_b[5]_PORT_B_write_enable, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_clock_0 = clk;
V1_q_b[5]_clock_1 = A1L5;
V1_q_b[5]_PORT_B_data_out = MEMORY(V1_q_b[5]_PORT_A_data_in_reg, V1_q_b[5]_PORT_B_data_in_reg, V1_q_b[5]_PORT_A_address_reg, V1_q_b[5]_PORT_B_address_reg, V1_q_b[5]_PORT_A_write_enable_reg, V1_q_b[5]_PORT_B_write_enable_reg, , , V1_q_b[5]_clock_0, V1_q_b[5]_clock_1, , , , );
V1_q_b[5] = V1_q_b[5]_PORT_B_data_out[0];


--E1L61 is MUX41A:inst3|DATAOUT[5]~826
--operation mode is normal

E1L61 = n0 & (V1_q_a[5] # n1) # !n0 & !n1 & E1L81;


--E1L81 is MUX41A:inst3|DATAOUT[5]~840
--operation mode is normal

E1L81 = LCELL(E1L61 & (Y1_q_a[5] # !n1) # !E1L61 & N1_q_a[5] & n1);