?? top.fit.rpt
字號:
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion -- Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+----------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error ; On ;
; Release clears before tri-states ; Off ;
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/EDA/multi-wave creator/top.fit.eqn.
+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/EDA/multi-wave creator/top.pin.
+-----------------------------------------------------------+
; Fitter Resource Usage Summary ;
+--------------------------------+--------------------------+
; Resource ; Usage ;
+--------------------------------+--------------------------+
; Logic cells ; 393 / 2,910 ( 13 % ) ;
; Registers ; 233 / 3,210 ( 7 % ) ;
; Total LABs ; 62 / 291 ( 21 % ) ;
; Logic elements in carry chains ; 69 ;
; User inserted logic cells ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 26 / 104 ( 25 % ) ;
; -- Clock pins ; 0 / 2 ( 0 % ) ;
; Global signals ; 8 ;
; M4Ks ; 3 / 13 ( 23 % ) ;
; Total memory bits ; 1,536 / 59,904 ( 2 % ) ;
; Total RAM block bits ; 13,824 / 59,904 ( 23 % ) ;
; Global clocks ; 8 / 8 ( 100 % ) ;
; Maximum fan-out node ; altera_internal_jtag~TDO ;
; Maximum fan-out ; 206 ;
; Total fan-out ; 1847 ;
; Average fan-out ; 4.31 ;
+--------------------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk ; 123 ; 2 ; 18 ; 14 ; 1 ; 22 ; 0 ; yes ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
; clk2 ; 124 ; 2 ; 16 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
; n0 ; 11 ; 1 ; 0 ; 9 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
; n1 ; 32 ; 1 ; 0 ; 3 ; 1 ; 16 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
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