LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SJCRT IS
	PORT(	CLK	:IN STD_LOGIC;
			DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE DACC OF SJCRT IS
COMPONENT data_rom2
	PORT(	address	:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
			inclock	:IN STD_LOGIC;
			q		:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
	SIGNAL 	Q1:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
	IF CLK'EVENT AND CLK='1' THEN Q1<=Q1+1;
		END IF;
END PROCESS;
u1:data_rom2 PORT MAP(address=>Q1,q=>DOUT,inclock=>CLK);
END;