; N/A           ; None        ; -3.108 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -3.108 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -3.223 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[4] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[4]    ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[0]    ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[5]    ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[3]    ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[2]    ; CLK      ;
; N/A           ; None        ; -3.226 ns ; CE      ; generator_acc6:U4|REG_Q[1]    ; CLK      ;
; N/A           ; None        ; -3.255 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[2] ; CLK      ;
; N/A           ; None        ; -3.255 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[5] ; CLK      ;
; N/A           ; None        ; -3.255 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[7] ; CLK      ;
; N/A           ; None        ; -3.539 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -3.539 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[2] ; CLK      ;
; N/A           ; None        ; -3.539 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -3.539 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[0] ; CLK      ;
; N/A           ; None        ; -3.646 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[0] ; CLK      ;
; N/A           ; None        ; -3.646 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[1] ; CLK      ;
; N/A           ; None        ; -3.646 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[6] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[0] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[2] ; CLK      ;
; N/A           ; None        ; -3.881 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -3.882 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -3.882 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -4.313 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -4.313 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[2] ; CLK      ;
; N/A           ; None        ; -4.313 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -4.313 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[0] ; CLK      ;
+---------------+-------------+-----------+---------+-------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 17 10:04:15 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sine_generator -c sine_generator --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 203.09 MHz between source register "generator_acc6:U4|REG_Q[3]" and destination register "generator_reg8:U7|TEMP_Q_1[4]" (period= 4.924 ns)
    Info: + Longest register to register delay is 4.768 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y11_N4; Fanout = 4; REG Node = 'generator_acc6:U4|REG_Q[3]'
        Info: 2: + IC(0.792 ns) + CELL(0.524 ns) = 1.316 ns; Loc. = LC_X45_Y11_N4; Fanout = 2; COMB Node = 'generator_adder:U3|add~137'
        Info: 3: + IC(0.000 ns) + CELL(0.449 ns) = 1.765 ns; Loc. = LC_X45_Y11_N6; Fanout = 24; COMB Node = 'generator_adder:U3|add~120'
        Info: 4: + IC(1.084 ns) + CELL(0.366 ns) = 3.215 ns; Loc. = LC_X45_Y12_N7; Fanout = 1; COMB Node = 'generator_sin:U6|Mux~1326'
        Info: 5: + IC(0.322 ns) + CELL(0.366 ns) = 3.903 ns; Loc. = LC_X45_Y12_N2; Fanout = 1; COMB Node = 'generator_sin:U6|Mux~1327'
        Info: 6: + IC(0.326 ns) + CELL(0.539 ns) = 4.768 ns; Loc. = LC_X45_Y12_N4; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[4]'
        Info: Total cell delay = 2.244 ns ( 47.06 % )
        Info: Total interconnect delay = 2.524 ns ( 52.94 % )
    Info: - Smallest clock skew is 0.010 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.872 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(1.605 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X45_Y12_N4; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[4]'
            Info: Total cell delay = 1.267 ns ( 44.12 % )
            Info: Total interconnect delay = 1.605 ns ( 55.88 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.862 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X44_Y11_N4; Fanout = 4; REG Node = 'generator_acc6:U4|REG_Q[3]'
            Info: Total cell delay = 1.267 ns ( 44.27 % )
            Info: Total interconnect delay = 1.595 ns ( 55.73 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "generator_reg6:U2|TEMP_Q_0[3]" (data pin = "CE", clock pin = "CLK") is 4.423 ns
    Info: + Longest pin to register delay is 7.275 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W7; Fanout = 16; PIN Node = 'CE'
        Info: 2: + IC(4.442 ns) + CELL(0.280 ns) = 5.809 ns; Loc. = LC_X46_Y11_N3; Fanout = 6; COMB Node = 'generator_and2:U8|O'
        Info: 3: + IC(0.761 ns) + CELL(0.705 ns) = 7.275 ns; Loc. = LC_X44_Y11_N0; Fanout = 2; REG Node = 'generator_reg6:U2|TEMP_Q_0[3]'
        Info: Total cell delay = 2.072 ns ( 28.48 % )
        Info: Total interconnect delay = 5.203 ns ( 71.52 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.862 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X44_Y11_N0; Fanout = 2; REG Node = 'generator_reg6:U2|TEMP_Q_0[3]'
        Info: Total cell delay = 1.267 ns ( 44.27 % )
        Info: Total interconnect delay = 1.595 ns ( 55.73 % )
Info: tco from clock "CLK" to destination pin "Q[6]" through register "generator_reg8:U7|TEMP_Q_1[6]" is 7.531 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.872 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.605 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X46_Y12_N3; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[6]'
        Info: Total cell delay = 1.267 ns ( 44.12 % )
        Info: Total interconnect delay = 1.605 ns ( 55.88 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.503 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X46_Y12_N3; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[6]'
        Info: 2: + IC(2.099 ns) + CELL(2.404 ns) = 4.503 ns; Loc. = PIN_V5; Fanout = 0; PIN Node = 'Q[6]'
        Info: Total cell delay = 2.404 ns ( 53.39 % )
        Info: Total interconnect delay = 2.099 ns ( 46.61 % )
Info: th for register "generator_reg6:U1|TEMP_Q_0[2]" (data pin = "DATA[2]", clock pin = "CLK") is -1.886 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.862 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X46_Y11_N4; Fanout = 3; REG Node = 'generator_reg6:U1|TEMP_Q_0[2]'
        Info: Total cell delay = 1.267 ns ( 44.27 % )
        Info: Total interconnect delay = 1.595 ns ( 55.73 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.848 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_N3; Fanout = 2; PIN Node = 'DATA[2]'
        Info: 2: + IC(3.529 ns) + CELL(0.085 ns) = 4.848 ns; Loc. = LC_X46_Y11_N4; Fanout = 3; REG Node = 'generator_reg6:U1|TEMP_Q_0[2]'
        Info: Total cell delay = 1.319 ns ( 27.21 % )
        Info: Total interconnect delay = 3.529 ns ( 72.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Apr 17 10:04:15 2008
    Info: Elapsed time: 00:00:01