{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 10:03:52 2008 " "Info: Processing started: Thu Apr 17 10:03:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sine_generator -c sine_generator " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sine_generator -c sine_generator" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sine_generator.vhd 16 8 " "Warning: Using design file sine_generator.vhd, which is not specified as a design file for the current project, but contains definitions for 16 design units and 8 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 generator_acc6-acc_arch " "Info: Found design unit 1: generator_acc6-acc_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 generator_mux-mux_arch " "Info: Found design unit 2: generator_mux-mux_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 103 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 generator_adder-add_anGen_arch " "Info: Found design unit 3: generator_adder-add_anGen_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 138 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 generator_and2-and_anGen_arch " "Info: Found design unit 4: generator_and2-and_anGen_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 168 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 generator_sin-sin_arch " "Info: Found design unit 5: generator_sin-sin_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 196 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 generator_reg6-reg_arch6 " "Info: Found design unit 6: generator_reg6-reg_arch6" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 300 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 generator_reg8-reg_arch8 " "Info: Found design unit 7: generator_reg8-reg_arch8" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 348 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 sine_generator-generator_arch " "Info: Found design unit 8: sine_generator-generator_arch" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 394 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 generator_acc6 " "Info: Found entity 1: generator_acc6" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 generator_mux " "Info: Found entity 2: generator_mux" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 92 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 generator_adder " "Info: Found entity 3: generator_adder" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 129 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 generator_and2 " "Info: Found entity 4: generator_and2" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 158 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 generator_sin " "Info: Found entity 5: generator_sin" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 186 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 generator_reg6 " "Info: Found entity 6: generator_reg6" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 288 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 generator_reg8 " "Info: Found entity 7: generator_reg8" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 336 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 sine_generator " "Info: Found entity 8: sine_generator" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 380 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sine_generator " "Info: Elaborating entity \"sine_generator\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "VAL1 sine_generator.vhd(451) " "Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(451): object \"VAL1\" declared but not used" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 451 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "VAL2 sine_generator.vhd(452) " "Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(452): object \"VAL2\" declared but not used" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 452 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "VAL3 sine_generator.vhd(453) " "Info (10035): Verilog HDL or VHDL information at sine_generator.vhd(453): object \"VAL3\" declared but not used" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 453 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_reg6 generator_reg6:U1 " "Info: Elaborating entity \"generator_reg6\" for hierarchy \"generator_reg6:U1\"" {  } { { "sine_generator.vhd" "U1" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 459 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_sin generator_sin:U6 " "Info: Elaborating entity \"generator_sin\" for hierarchy \"generator_sin:U6\"" {  } { { "sine_generator.vhd" "U6" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 467 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "sine_generator.vhd(267) " "Info (10425): VHDL Case Statement information at sine_generator.vhd(267): OTHERS choice is never selected" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 267 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_adder generator_adder:U3 " "Info: Elaborating entity \"generator_adder\" for hierarchy \"generator_adder:U3\"" {  } { { "sine_generator.vhd" "U3" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 483 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_acc6 generator_acc6:U4 " "Info: Elaborating entity \"generator_acc6\" for hierarchy \"generator_acc6:U4\"" {  } { { "sine_generator.vhd" "U4" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 489 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_reg8 generator_reg8:U7 " "Info: Elaborating entity \"generator_reg8\" for hierarchy \"generator_reg8:U7\"" {  } { { "sine_generator.vhd" "U7" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 497 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_and2 generator_and2:U8 " "Info: Elaborating entity \"generator_and2\" for hierarchy \"generator_and2:U8\"" {  } { { "sine_generator.vhd" "U8" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 505 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[7\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[7\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[6\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[6\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[5\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[5\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[4\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[4\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[3\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[3\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[2\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[2\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[1\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[1\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "generator_sin:U6\|Q\[0\] " "Warning: Converting TRI node \"generator_sin:U6\|Q\[0\]\" that feeds logic to a wire" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 190 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "60 " "Info: Implemented 60 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 17 10:03:55 2008 " "Info: Processing ended: Thu Apr 17 10:03:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}