-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/31/2007 10:55:59"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	ram_256 IS
    PORT (
	we : IN std_logic;
	oe : IN std_logic;
	cs : IN std_logic;
	adr : IN std_logic_vector(7 DOWNTO 0);
	data_in : IN std_logic_vector(7 DOWNTO 0);
	data_out : OUT std_logic_vector(7 DOWNTO 0)
	);
END ram_256;

ARCHITECTURE structure OF ram_256 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_we : std_logic;
SIGNAL ww_oe : std_logic;
SIGNAL ww_cs : std_logic;
SIGNAL ww_adr : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_data_in : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL \we~combout\ : std_logic;
SIGNAL \data_in[0]~combout\ : std_logic;
SIGNAL \cs~combout\ : std_logic;
SIGNAL \adr[0]~combout\ : std_logic;
SIGNAL \sram[0][0]~45\ : std_logic;
SIGNAL \sram[0][0]\ : std_logic;
SIGNAL \oe~combout\ : std_logic;
SIGNAL \process1~0\ : std_logic;
SIGNAL \data_in[1]~combout\ : std_logic;
SIGNAL \sram[0][1]\ : std_logic;
SIGNAL \data_in[2]~combout\ : std_logic;
SIGNAL \sram[0][2]\ : std_logic;
SIGNAL \data_in[3]~combout\ : std_logic;
SIGNAL \sram[0][3]\ : std_logic;
SIGNAL \data_in[4]~combout\ : std_logic;
SIGNAL \sram[0][4]\ : std_logic;
SIGNAL \data_in[5]~combout\ : std_logic;
SIGNAL \sram[0][5]\ : std_logic;
SIGNAL \data_in[6]~combout\ : std_logic;
SIGNAL \sram[0][6]\ : std_logic;
SIGNAL \data_in[7]~combout\ : std_logic;
SIGNAL \sram[0][7]\ : std_logic;
SIGNAL \ALT_INV_we~combout\ : std_logic;

BEGIN

ww_we <= we;
ww_oe <= oe;
ww_cs <= cs;
ww_adr <= adr;
ww_data_in <= data_in;
data_out <= ww_data_out;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_we~combout\ <= NOT \we~combout\;

\we~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_we,
	combout => \we~combout\);

\data_in[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_data_in(0),
	combout => \data_in[0]~combout\);

\cs~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_cs,
	combout => \cs~combout\);

\adr[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_adr(0),
	combout => \adr[0]~combout\);

\sram[0][0]~45_I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][0]~45\ = !\we~combout\ & (!\cs~combout\ & !\adr[0]~combout\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0005",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \we~combout\,
	datac => \cs~combout\,
	datad => \adr[0]~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \sram[0][0]~45\);

\sram[0][0]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][0]\ = DFFEAS(GND, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, \data_in[0]~combout\, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_we~combout\,
	datac => \data_in[0]~combout\,
	aclr => GND,
	sload => VCC,
	ena => \sram[0][0]~45\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \sram[0][0]\);

\oe~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_oe,
	combout => \oe~combout\);

\process1~0_I\ : cyclone_lcell
-- Equation(s):
-- \process1~0\ = !\cs~combout\ & !\oe~combout\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "000F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => \cs~combout\,
	datad => \oe~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \process1~0\);

\data_in[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_data_in(1),
	combout => \data_in[1]~combout\);

\sram[0][1]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][1]\ = DFFEAS(\data_in[1]~combout\, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF00",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_we~combout\,
	datad => \data_in[1]~combout\,
	aclr => GND,
	ena => \sram[0][0]~45\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \sram[0][1]\);

\data_in[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_data_in(2),
	combout => \data_in[2]~combout\);

\sram[0][2]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][2]\ = DFFEAS(\data_in[2]~combout\, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF00",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_we~combout\,
	datad => \data_in[2]~combout\,
	aclr => GND,
	ena => \sram[0][0]~45\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \sram[0][2]\);

\data_in[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_data_in(3),
	combout => \data_in[3]~combout\);

\sram[0][3]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][3]\ = DFFEAS(GND, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, \data_in[3]~combout\, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_we~combout\,
	datac => \data_in[3]~combout\,
	aclr => GND,
	sload => VCC,
	ena => \sram[0][0]~45\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \sram[0][3]\);

\data_in[4]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_data_in(4),
	combout => \data_in[4]~combout\);

\sram[0][4]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][4]\ = DFFEAS(\data_in[4]~combout\, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF00",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_we~combout\,
	datad => \data_in[4]~combout\,
	aclr => GND,
	ena => \sram[0][0]~45\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \sram[0][4]\);

\data_in[5]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,