?? ram_256.vho
字號:
oe => GND,
padio => ww_data_in(5),
combout => \data_in[5]~combout\);
\sram[0][5]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][5]\ = DFFEAS(GND, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, \data_in[5]~combout\, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "0000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
clk => \ALT_INV_we~combout\,
datac => \data_in[5]~combout\,
aclr => GND,
sload => VCC,
ena => \sram[0][0]~45\,
devclrn => ww_devclrn,
devpor => ww_devpor,
regout => \sram[0][5]\);
\data_in[6]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_data_in(6),
combout => \data_in[6]~combout\);
\sram[0][6]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][6]\ = DFFEAS(GND, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, \data_in[6]~combout\, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "0000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
clk => \ALT_INV_we~combout\,
datac => \data_in[6]~combout\,
aclr => GND,
sload => VCC,
ena => \sram[0][0]~45\,
devclrn => ww_devclrn,
devpor => ww_devpor,
regout => \sram[0][6]\);
\data_in[7]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_data_in(7),
combout => \data_in[7]~combout\);
\sram[0][7]~I\ : cyclone_lcell
-- Equation(s):
-- \sram[0][7]\ = DFFEAS(\data_in[7]~combout\, !GLOBAL(\we~combout\), VCC, , \sram[0][0]~45\, , , , )
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "FF00",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
clk => \ALT_INV_we~combout\,
datad => \data_in[7]~combout\,
aclr => GND,
ena => \sram[0][0]~45\,
devclrn => ww_devclrn,
devpor => ww_devpor,
regout => \sram[0][7]\);
\adr[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(1));
\adr[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(2));
\adr[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(3));
\adr[4]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(4));
\adr[5]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(5));
\adr[6]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(6));
\adr[7]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_adr(7));
\data_out[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][0]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(0));
\data_out[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][1]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(1));
\data_out[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][2]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(2));
\data_out[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][3]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(3));
\data_out[4]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][4]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(4));
\data_out[5]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][5]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(5));
\data_out[6]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][6]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(6));
\data_out[7]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => \sram[0][7]\,
oe => \process1~0\,
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
padio => ww_data_out(7));
END structure;
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