library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY ram_256 IS
generic (k: integer:=256;
         w: integer:=8);
	PORT(we,oe,cs		: IN	STD_LOGIC;
		adr	: IN	STD_LOGIC_VECTOR(w-1 DOWNTO 0);
		data_in	: IN	STD_LOGIC_VECTOR(w-1 DOWNTO 0);
	   data_out	: out	STD_LOGIC_VECTOR(w-1 DOWNTO 0));
END ram_256;

ARCHITECTURE a OF ram_256 IS
	subtype word is STD_LOGIC_VECTOR(w-1 DOWNTO 0);
	type memory is array(0 to 2**k) of word;
	SIGNAL sram : memory;
	SIGNAL adr_in : integer range 0 to 2**w-1;
	signal din_change,wr_rise: time :=0 ps;
	
BEGIN

 adr_in<=conv_integer(adr);
  process(we)
    begin 
      if  we'event and we='0'  then 
        if cs='0' and we='0'   then 
        sram(adr_in)<=data_in after 2 ns;
        end if;  
      end if;
     wr_rise <= now;
     assert(NOW-din_change>=800 ps)
     report "setup error din(sram)"
     severity warning;
   end process;
  process(oe,cs)
    begin 
      if  oe='0' and cs='0'  then 
       data_out<=sram(adr_in) after 3 ns;
      else
       data_out<="ZZZZZZZZ" after 4 ns;
      end if;
   end process;
  process(data_in)
    begin 
     din_change <= now;
     assert(NOW-wr_rise>=300 ps)
     report "hold error din(sram)"
     severity warning;
   end process;
END a;