?? my_dq.v
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// megafunction wizard: %ALTDQ%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altdq
// ============================================================
// File Name: MY_DQ.v
// Megafunction Name(s):
// altdq
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//altdq DDIOINCLK_INPUT="NEGATED_INCLK" DEVICE_FAMILY="Stratix" NUMBER_OF_DQ=8 OE_REG="REGISTERED" POWER_UP_HIGH="OFF" datain_h datain_l dataout_h dataout_l inclock oe outclock padio
//VERSION_BEGIN 4.1 cbx_altdq 2004:05:07:17:19:20:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ VERSION_END
//synthesis_resources = stratix_io 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module MY_DQ_dq_4rg
(
datain_h,
datain_l,
dataout_h,
dataout_l,
inclock,
oe,
outclock,
padio) /* synthesis synthesis_clearbox=1 */;
input [7:0] datain_h;
input [7:0] datain_l;
output [7:0] dataout_h;
output [7:0] dataout_l;
input inclock;
input oe;
input outclock;
inout [7:0] padio;
wire [7:0] wire_dq_ioa_datain;
wire [7:0] wire_dq_ioa_ddiodatain;
wire [7:0] wire_dq_ioa_ddioregout;
wire [7:0] wire_dq_ioa_regout;
stratix_io dq_ioa_0
(
.combout(),
.datain(wire_dq_ioa_datain[0:0]),
.ddiodatain(wire_dq_ioa_ddiodatain[0:0]),
.ddioregout(wire_dq_ioa_ddioregout[0:0]),
.dqsundelayedout(),
.inclk((~ inclock)),
.oe(oe),
.outclk(outclock),
.padio(padio[0:0]),
.regout(wire_dq_ioa_regout[0:0])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.areset(1'b0),
.delayctrlin(1'b0),
.inclkena(1'b1),
.outclkena(1'b1),
.sreset(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devoe(),
.devpor()
// synopsys translate_on
);
defparam
dq_ioa_0.ddio_mode = "bidir",
dq_ioa_0.extend_oe_disable = "false",
dq_ioa_0.input_async_reset = "none",
dq_ioa_0.input_power_up = "low",
dq_ioa_0.input_register_mode = "register",
dq_ioa_0.oe_async_reset = "none",
dq_ioa_0.oe_power_up = "low",
dq_ioa_0.oe_register_mode = "register",
dq_ioa_0.operation_mode = "bidir",
dq_ioa_0.output_async_reset = "none",
dq_ioa_0.output_power_up = "low",
dq_ioa_0.output_register_mode = "register",
dq_ioa_0.lpm_type = "stratix_io";
stratix_io dq_ioa_1
(
.combout(),
.datain(wire_dq_ioa_datain[1:1]),
.ddiodatain(wire_dq_ioa_ddiodatain[1:1]),
.ddioregout(wire_dq_ioa_ddioregout[1:1]),
.dqsundelayedout(),
.inclk((~ inclock)),
.oe(oe),
.outclk(outclock),
.padio(padio[1:1]),
.regout(wire_dq_ioa_regout[1:1])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.areset(1'b0),
.delayctrlin(1'b0),
.inclkena(1'b1),
.outclkena(1'b1),
.sreset(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devoe(),
.devpor()
// synopsys translate_on
);
defparam
dq_ioa_1.ddio_mode = "bidir",
dq_ioa_1.extend_oe_disable = "false",
dq_ioa_1.input_async_reset = "none",
dq_ioa_1.input_power_up = "low",
dq_ioa_1.input_register_mode = "register",
dq_ioa_1.oe_async_reset = "none",
dq_ioa_1.oe_power_up = "low",
dq_ioa_1.oe_register_mode = "register",
dq_ioa_1.operation_mode = "bidir",
dq_ioa_1.output_async_reset = "none",
dq_ioa_1.output_power_up = "low",
dq_ioa_1.output_register_mode = "register",
dq_ioa_1.lpm_type = "stratix_io";
stratix_io dq_ioa_2
(
.combout(),
.datain(wire_dq_ioa_datain[2:2]),
.ddiodatain(wire_dq_ioa_ddiodatain[2:2]),
.ddioregout(wire_dq_ioa_ddioregout[2:2]),
.dqsundelayedout(),
.inclk((~ inclock)),
.oe(oe),
.outclk(outclock),
.padio(padio[2:2]),
.regout(wire_dq_ioa_regout[2:2])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.areset(1'b0),
.delayctrlin(1'b0),
.inclkena(1'b1),
.outclkena(1'b1),
.sreset(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devoe(),
.devpor()
// synopsys translate_on
);
defparam
dq_ioa_2.ddio_mode = "bidir",
dq_ioa_2.extend_oe_disable = "false",
dq_ioa_2.input_async_reset = "none",
dq_ioa_2.input_power_up = "low",
dq_ioa_2.input_register_mode = "register",
dq_ioa_2.oe_async_reset = "none",
dq_ioa_2.oe_power_up = "low",
dq_ioa_2.oe_register_mode = "register",
dq_ioa_2.operation_mode = "bidir",
dq_ioa_2.output_async_reset = "none",
dq_ioa_2.output_power_up = "low",
dq_ioa_2.output_register_mode = "register",
dq_ioa_2.lpm_type = "stratix_io";
stratix_io dq_ioa_3
(
.combout(),
.datain(wire_dq_ioa_datain[3:3]),
.ddiodatain(wire_dq_ioa_ddiodatain[3:3]),
.ddioregout(wire_dq_ioa_ddioregout[3:3]),
.dqsundelayedout(),
.inclk((~ inclock)),
.oe(oe),
.outclk(outclock),
.padio(padio[3:3]),
.regout(wire_dq_ioa_regout[3:3])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.areset(1'b0),
.delayctrlin(1'b0),
.inclkena(1'b1),
.outclkena(1'b1),
.sreset(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devoe(),
.devpor()
// synopsys translate_on
);
defparam
dq_ioa_3.ddio_mode = "bidir",
dq_ioa_3.extend_oe_disable = "false",
dq_ioa_3.input_async_reset = "none",
dq_ioa_3.input_power_up = "low",
dq_ioa_3.input_register_mode = "register",
dq_ioa_3.oe_async_reset = "none",
dq_ioa_3.oe_power_up = "low",
dq_ioa_3.oe_register_mode = "register",
dq_ioa_3.operation_mode = "bidir",
dq_ioa_3.output_async_reset = "none",
dq_ioa_3.output_power_up = "low",
dq_ioa_3.output_register_mode = "register",
dq_ioa_3.lpm_type = "stratix_io";
stratix_io dq_ioa_4
(
.combout(),
.datain(wire_dq_ioa_datain[4:4]),
.ddiodatain(wire_dq_ioa_ddiodatain[4:4]),
.ddioregout(wire_dq_ioa_ddioregout[4:4]),
.dqsundelayedout(),
.inclk((~ inclock)),
.oe(oe),
.outclk(outclock),
.padio(padio[4:4]),
.regout(wire_dq_ioa_regout[4:4])
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