Timing Analyzer report for image
Mon Apr 21 09:41:48 2008
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'pll:U3|altpll:altpll_component|_clk0'
  6. Clock Setup: 'clk'
  7. Clock Hold: 'pll:U3|altpll:altpll_component|_clk0'
  8. Clock Hold: 'clk'
  9. tsu
 10. tco
 11. th
 12. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                  ;
+-----------------------------------------------------+-----------+----------------------------------+-------------+---------------------------------+----------------------------------------+--------------------------------------+--------------------------------------+--------------+
; Type                                                ; Slack     ; Required Time                    ; Actual Time ; From                            ; To                                     ; From Clock                           ; To Clock                             ; Failed Paths ;
+-----------------------------------------------------+-----------+----------------------------------+-------------+---------------------------------+----------------------------------------+--------------------------------------+--------------------------------------+--------------+
; Worst-case tsu                                      ; N/A       ; None                             ; 4.271 ns    ; rxd                             ; rs232_r:U1|rcv:u2|clk1x_enable         ;                                      ; clk                                  ; 0            ;
; Worst-case tco                                      ; N/A       ; None                             ; 16.710 ns   ; rs232_t:u5|send:u2|dout         ; txd                                    ; clk                                  ;                                      ; 0            ;
; Worst-case th                                       ; N/A       ; None                             ; -0.727 ns   ; rxd                             ; rs232_r:U1|rcv:u2|rxd1                 ;                                      ; clk                                  ; 0            ;
; Clock Setup: 'pll:U3|altpll:altpll_component|_clk0' ; -6.783 ns ; 54.00 MHz ( period = 18.518 ns ) ; N/A         ; rs232_r:U1|rcv:u2|rgb_sel[2]    ; image1:U2|out_g_e[0]                   ; clk                                  ; pll:U3|altpll:altpll_component|_clk0 ; 283          ;
; Clock Setup: 'clk'                                  ; -5.601 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A         ; image1:U2|count1[6]             ; rs232_t:u5|dataout[1]                  ; pll:U3|altpll:altpll_component|_clk0 ; clk                                  ; 9            ;
; Clock Hold: 'clk'                                   ; -7.956 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A         ; rs232_t:u5|send:u2|clk1x_enable ; rs232_t:u5|send:u2|no_bits_sent[0]     ; clk                                  ; clk                                  ; 32           ;
; Clock Hold: 'pll:U3|altpll:altpll_component|_clk0'  ; 0.862 ns  ; 54.00 MHz ( period = 18.518 ns ) ; N/A         ; image1:U2|level3in[6]           ; image1:U2|shinningblock:U2|out2_r_e[6] ; pll:U3|altpll:altpll_component|_clk0 ; pll:U3|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                        ;           ;                                  ;             ;                                 ;                                        ;                                      ;                                      ; 324          ;
+-----------------------------------------------------+-----------+----------------------------------+-------------+---------------------------------+----------------------------------------+--------------------------------------+--------------------------------------+--------------+