Fitter report for image
Mon Apr 21 09:41:41 2008
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. Bidir Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. PLL Summary
 14. PLL Usage
 15. Output Pin Default Load For Reported TCO
 16. Fitter Resource Utilization by Entity
 17. Delay Chain Summary
 18. Pad To Core Delay Chain Fanout
 19. Control Signals
 20. Global & Other Fast Signals
 21. Non-Global High Fan-Out Signals
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Mon Apr 21 09:41:41 2008         ;
; Quartus II Version    ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name         ; image                                         ;
; Top-level Entity Name ; image                                         ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C6T144C8                                   ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 991 / 5,980 ( 16 % )                          ;
; Total pins            ; 60 / 98 ( 61 % )                              ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                            ;
; Total PLLs            ; 1 / 2 ( 50 % )                                ;
+-----------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C6T144C8                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;