; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                 ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                 ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                 ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                 ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                 ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                 ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                 ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                 ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                 ;
; DEVICE_FAMILY                 ; Cyclone           ; Untyped                 ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY              ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY            ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE            ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE          ;
+-------------------------------+-------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/study/畢業設計/韓健程序/cyclic/image.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Apr 21 09:40:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off image -c image
Info: Found 2 design units, including 1 entities, in source file image.vhd
    Info: Found design unit 1: image-rtl
    Info: Found entity 1: image
Info: Found 2 design units, including 1 entities, in source file image1.vhd
    Info: Found design unit 1: image1-rtl
    Info: Found entity 1: image1
Info: Found 2 design units, including 1 entities, in source file shinningblock.vhd
    Info: Found design unit 1: shinningblock-rtl
    Info: Found entity 1: shinningblock
Info: Found 2 design units, including 1 entities, in source file rs232_r.vhd
    Info: Found design unit 1: rs232_r-rtl
    Info: Found entity 1: rs232_r
Info: Found 2 design units, including 1 entities, in source file pll1.vhd
    Info: Found design unit 1: pll1-counter
    Info: Found entity 1: pll1
Info: Found 2 design units, including 1 entities, in source file rcv.vhd
    Info: Found design unit 1: rcv-v1
    Info: Found entity 1: rcv
Info: Found 2 design units, including 1 entities, in source file amp.vhd
    Info: Found design unit 1: amp-rtl
    Info: Found entity 1: amp
Info: Found 2 design units, including 1 entities, in source file count.vhd
    Info: Found design unit 1: count-rtl
    Info: Found entity 1: count
Info: Found 2 design units, including 1 entities, in source file rs232_t.vhd
    Info: Found design unit 1: rs232_t-rtl
    Info: Found entity 1: rs232_t
Info: Found 2 design units, including 1 entities, in source file send.vhd
    Info: Found design unit 1: send-rtl
    Info: Found entity 1: send
Info: Elaborating entity "image" for the top level hierarchy
Info: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pll-SYN
    Info: Found entity 1: pll
Info: Elaborating entity "pll" for hierarchy "pll:U3"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pll:U3|altpll:altpll_component"
Info: Elaborating entity "amp" for hierarchy "amp:U4"
Info: Elaborating entity "count" for hierarchy "amp:U4|count:U1"
Info: Elaborating entity "rs232_t" for hierarchy "rs232_t:u5"
Info: Elaborating entity "pll1" for hierarchy "rs232_t:u5|pll1:u1"
Info: Elaborating entity "send" for hierarchy "rs232_t:u5|send:u2"
Info: Elaborating entity "rs232_r" for hierarchy "rs232_r:U1"
Info: Elaborating entity "rcv" for hierarchy "rs232_r:U1|rcv:u2"
Info: Elaborating entity "image1" for hierarchy "image1:U2"
Info: (10035) Verilog HDL or VHDL information at image1.vhd(65): object "data_g" declared but not used
Info: (10035) Verilog HDL or VHDL information at image1.vhd(66): object "data_b" declared but not used
Info: (10035) Verilog HDL or VHDL information at image1.vhd(88): object "levelin1" declared but not used
Info: (10035) Verilog HDL or VHDL information at image1.vhd(89): object "levelin2" declared but not used
Info: Elaborating entity "shinningblock" for hierarchy "image1:U2|shinningblock:U2"
Info: VHDL Case Statement information at shinningblock.vhd(292): OTHERS choice is never selected
Info: Power-up level of register "image1:U2|mode" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|mode" with stuck data_in port to stuck value VCC
Info: Power-up level of register "image1:U2|outsel" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|outsel" with stuck data_in port to stuck value VCC
Info: Power-up level of register "image1:U2|size[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|size[3]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "image1:U2|size[2]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|size[2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "image1:U2|chose[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "image1:U2|chose[1]" with stuck data_in port to stuck value GND
Info: Power-up level of register "image1:U2|chose[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|chose[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "image1:U2|refresh[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "image1:U2|refresh[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "image1:U2|pos[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "image1:U2|pos[2]" with stuck data_in port to stuck value GND
Info: Power-up level of register "image1:U2|pos[1]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|pos[1]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "image1:U2|pos[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|pos[0]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "image1:U2|startin" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "image1:U2|startin" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "image1:U2|size[0]" merged to single register "image1:U2|size[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[7]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[7]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[7]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[7]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[7]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[7]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[7]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[7]"