?? image1.vhd
字號:
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity image1 is
PORT
(
clk : IN std_logic;
ctrl : in std_logic;
hs_out : OUT std_logic;
de_out : BUFFER std_logic;
vs_out : OUT std_logic;
pixs_out : OUT std_logic;
trigger : OUT std_logic;
rgb_sel : IN std_logic_vector (7 downto 0);
level1 : IN std_logic_vector (7 downto 0);
level2 : IN std_logic_vector (7 downto 0);
level3 : IN std_logic_vector (7 downto 0);
time1 : IN std_logic_vector (7 downto 0);
time2 : IN std_logic_vector (7 downto 0);
time3 : IN std_logic_vector (7 downto 0);
panel_sel : IN std_logic_vector (7 downto 0);
auto : IN std_logic_vector (7 downto 0);
levellow : IN std_logic_vector (7 downto 0);
levelhigh : IN std_logic_vector (7 downto 0);
datain : out std_logic_vector(7 downto 0);
out_r_e : OUT std_logic_vector(7 DOWNTO 0);
out_g_e : OUT std_logic_vector(7 DOWNTO 0);
out_b_e : OUT std_logic_vector(7 DOWNTO 0);
out_r_o : OUT std_logic_vector(7 DOWNTO 0);
out_g_o : OUT std_logic_vector(7 DOWNTO 0);
out_b_o : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=640; -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=20; -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=20; -- horizontal back porch
CONSTANT VAC:integer:=1024; -- vertical active pixels
CONSTANT VSY:integer:=25; -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=25; -- vertical back porch
END image1;
ARCHITECTURE rtl OF image1 IS
SIGNAL VTOT :integer;
SIGNAL HTOT :integer;
SIGNAL hb : std_logic;
SIGNAL hs : std_logic;
SIGNAL vb : std_logic;
SIGNAL vs : std_logic;
SIGNAL clken_vcount: std_logic;
SIGNAL clken_fcount: std_logic;
SIGNAL out1_r_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out1_r_o : std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_o : std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_o : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_e : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_o : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_o : std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_o : std_logic_vector(7 DOWNTO 0);
SIGNAL data_g : std_logic_vector(7 DOWNTO 0);
SIGNAL data_b : std_logic_vector(7 DOWNTO 0);
SIGNAL vcountreg : std_logic_vector(11 DOWNTO 0);
SIGNAL hcountreg : std_logic_vector(10 DOWNTO 0);
SIGNAL mode : std_logic;
SIGNAL startin : std_logic;
SIGNAL time1in : std_logic_vector(3 DOWNTO 0);
SIGNAL time2in : std_logic_vector(3 DOWNTO 0);
SIGNAL time3in : std_logic_vector(3 DOWNTO 0);
SIGNAL level1in : std_logic_vector(7 DOWNTO 0);
SIGNAL level2in : std_logic_vector(7 DOWNTO 0);
SIGNAl level3in : std_logic_vector(7 DOWNTO 0);
SIGNAL size : std_logic_vector(3 DOWNTO 0);
SIGNAL chose : std_logic_vector(2 DOWNTO 0);
SIGNAL refresh : std_logic_vector(1 DOWNTO 0);
signal pos : std_logic_vector(3 DOWNTO 0);
signal outsel : std_logic;
SIGNAL d1in : std_logic_vector(7 DOWNTO 0);
SIGNAL d2in : std_logic_vector(7 DOWNTO 0);
SIGNAL d3in : std_logic_vector(7 DOWNTO 0);
signal time1set : std_logic_vector(3 downto 0);
signal time2set : std_logic_vector(3 downto 0);
signal time3set : std_logic_vector(3 downto 0);
SIGNAL levelin1 : std_logic_vector(7 DOWNTO 0);
SIGNAL levelin2 : std_logic_vector(7 DOWNTO 0);
SIGNAL levellowin : std_logic_vector(7 downto 0);
SIGNAL levelhighin : std_logic_vector(7 downto 0);
signal count1 : std_logic_vector(7 downto 0);
COMPONENT shinningblock IS
PORT
(
clk : IN std_logic;
vcount : IN std_logic_vector(11 DOWNTO 0);
hcount : IN std_logic_vector(10 DOWNTO 0);
clken_fcount: IN std_logic;
mode : IN std_logic;
startin: IN std_logic;
outsel : IN std_logic;
refresh: IN std_logic_vector(1 DOWNTO 0);
time1 : IN std_logic_vector(3 DOWNTO 0);
time2 : IN std_logic_vector(3 DOWNTO 0);
time3 : IN std_logic_vector(3 DOWNTO 0);
level1 : IN std_logic_vector(7 DOWNTO 0);
level2 : IN std_logic_vector(7 DOWNTO 0);
level3 : IN std_logic_vector(7 DOWNTO 0);
size : IN std_logic_vector(3 DOWNTO 0);
pos : IN std_logic_vector(3 DOWNTO 0);
trigger: OUT std_logic;
out_r_e: OUT std_logic_vector(7 DOWNTO 0);
out_g_e: OUT std_logic_vector(7 DOWNTO 0);
out_b_e: OUT std_logic_vector(7 DOWNTO 0);
out_r_o: OUT std_logic_vector(7 DOWNTO 0);
out_g_o: OUT std_logic_vector(7 DOWNTO 0);
out_b_o: OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
BEGIN
process(clk,auto)
begin
if clk'event and clk = '1' then
if auto = "00000010" then --自動測量參數設置
startin <= '1';
mode <= '1';
outsel <= '1';
time1in <= "0010";
time2in <= "0010";
time3in <= "0010";
size <= "1111";
level1in <= levellowin;
level2in <= levelhighin;
chose <= "001";
refresh <= "00";
level3in <= levellowin;
pos <= "0011";
else --手動測量的各個參數
startin <= '1';
mode <= '1';
outsel <= '1';
time1in <= time1set;
time2in <= time2set;
time3in <= time3set;
size <= "1100";
level1in <= d1in;
level2in <= d2in;
chose <= "001";
refresh <= "00";
level3in <= d3in;
pos <= "0011";
end if;
end if;
end process;
process(ctrl)
begin
if ctrl'event and ctrl = '1' then
if count1 = "11111111" then
count1 <= "00000000";
else
count1 <= count1 + "00000001";
end if;
end if;
end process; --when 19 grayscale,count1 = "10101011"
process(clk) --手動測量三個灰度級對應的時間轉換（8bit to 4bit）
begin --該time數據代表灰度級level維持的幀數
if clk'event and clk = '1' then
case time1 is
WHEN "00000000"=> time1set <= "0000";
WHEN "10000000"=> time1set <= "0001";
WHEN "01000000"=> time1set <= "0010";
WHEN "11000000"=> time1set <= "0011";
WHEN "00100000"=> time1set <= "0100";
WHEN "10100000"=> time1set <= "0101";
WHEN "01100000"=> time1set <= "0110";
WHEN "11100000"=> time1set <= "0111";
WHEN "00010000"=> time1set <= "1000";
WHEN "10010000"=> time1set <= "1001";
WHEN "01010000"=> time1set <= "1010";
when "11010000"=> time1set <= "1011";
when others => time1set <= "0001";
end case;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
case time2 is
WHEN "00000000"=> time2set <= "0000";
WHEN "10000000"=> time2set <= "0001";
WHEN "01000000"=> time2set <= "0010";
WHEN "11000000"=> time2set <= "0011";
WHEN "00100000"=> time2set <= "0100";
WHEN "10100000"=> time2set <= "0101";
WHEN "01100000"=> time2set <= "0110";
WHEN "11100000"=> time2set <= "0111";
WHEN "00010000"=> time2set <= "1000";
WHEN "10010000"=> time2set <= "1001";
WHEN "01010000"=> time2set <= "1010";
when "11010000"=> time2set <= "1011";
when others => time2set <= "0001";
end case;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
case time3 is
WHEN "00000000"=> time3set <= "0000";
WHEN "10000000"=> time3set <= "0001";
WHEN "01000000"=> time3set <= "0010";
WHEN "11000000"=> time3set <= "0011";
WHEN "00100000"=> time3set <= "0100";
WHEN "10100000"=> time3set <= "0101";
WHEN "01100000"=> time3set <= "0110";
WHEN "11100000"=> time3set <= "0111";
WHEN "00010000"=> time3set <= "1000";
WHEN "10010000"=> time3set <= "1001";
WHEN "01010000"=> time3set <= "1010";
when "11010000"=> time3set <= "1011";
when others => time3set <= "0001";
end case;
end if;
end process;
process(clk) --圖像灰度級level的數據轉換
begin --level數據互補換位轉換成真正的二進制數
if clk'event and clk = '1' then
d1in(0) <= level1(7);
d1in(1) <= level1(6);
d1in(2) <= level1(5);
d1in(3) <= level1(4);
d1in(4) <= level1(3);
d1in(5) <= level1(2);
d1in(6) <= level1(1);
d1in(7) <= level1(0);
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
d2in(0) <= level2(7);
d2in(1) <= level2(6);
d2in(2) <= level2(5);
d2in(3) <= level2(4);
d2in(4) <= level2(3);
d2in(5) <= level2(2);
d2in(6) <= level2(1);
d2in(7) <= level2(0);
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
d3in(0) <= level3(7);
d3in(1) <= level3(6);
d3in(2) <= level3(5);
d3in(3) <= level3(4);
d3in(4) <= level3(3);
d3in(5) <= level3(2);
d3in(6) <= level3(1);
d3in(7) <= level3(0);
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
levellowin(0) <= levellow(7);
levellowin(1) <= levellow(6);
levellowin(2) <= levellow(5);
levellowin(3) <= levellow(4);
levellowin(4) <= levellow(3);
levellowin(5) <= levellow(2);
levellowin(6) <= levellow(1);
levellowin(7) <= levellow(0);
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
levelhighin(0) <= levelhigh(7);
levelhighin(1) <= levelhigh(6);
levelhighin(2) <= levelhigh(5);
levelhighin(3) <= levelhigh(4);
levelhighin(4) <= levelhigh(3);
levelhighin(5) <= levelhigh(2);
levelhighin(6) <= levelhigh(1);
levelhighin(7) <= levelhigh(0);
end if;
end process;
--產生行同步脈沖和行de
hcount: BLOCK
SIGNAL hz : std_logic;
BEGIN
PROCESS (clk,hz)
BEGIN
IF (hz = '1') THEN
hcountreg <= (OTHERS =>'0');
ELSIF clk'event AND clk = '1' THEN
hcountreg <= hcountreg +1;
END IF;
END PROCESS;
hb <= '1' when hcountreg >=HBP+HSY AND hcountreg <HBP+HSY+HAC
ELSE '0';
hs <='1' when hcountreg >=HSY AND hcountreg < HTOT
ELSE '0';
hz <= '1' when hcountreg = HTOT ELSE '0';
END BLOCK hcount;
--判斷行脈沖上升延，產生列起始信號
vstart : BLOCK
SIGNAL inputa : std_logic;
SIGNAL inputb : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputb <= inputa;
inputa <= NOT hs;
END IF;
END PROCESS;
clken_vcount <= NOT inputb AND inputa;
END BLOCK vstart;
--產生列同步和de
vcount : BLOCK
SIGNAL vz : std_logic;
BEGIN
PROCESS (clk,vz)
BEGIN
IF(vz='1')THEN
vcountreg <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clken_vcount = '1' THEN
vcountreg <= vcountreg +1;
END IF;
END IF;
END PROCESS;
vb <= '1' when vcountreg >=VBP+VSY AND vcountreg < VBP+VSY+VAC
ELSE '0';
vs <='1' when vcountreg >=VSY AND vcountreg < VTOT
ELSE '0';
vz <= '1' when vcountreg = VTOT ELSE '0';
END BLOCK vcount;
--判斷列脈沖上升延，產生幀起始信號
fstart : BLOCK
SIGNAL inputc : std_logic;
SIGNAL inputd : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputd <= inputc;
inputc <= NOT vs;
END IF;
END PROCESS;
clken_fcount <= NOT inputd AND inputc;
END BLOCK fstart;
U2: shinningblock
PORT MAP
(
clk => clk,
vcount => vcountreg,
hcount => hcountreg,
clken_fcount => clken_fcount,
mode => mode,
startin => startin,
outsel => outsel,
refresh => refresh,
time1 => time1in,
time2 => time2in,
time3 => time3in,
level1 => level1in,
level2 => level2in,
level3 => level3in,
size => size,
pos => pos,
trigger => trigger,
out_r_e => out2_r_e,
out_g_e => out2_g_e,
out_b_e => out2_b_e,
out_r_o => out2_r_o,
out_g_o => out2_g_o,
out_b_o => out2_b_o
);
process(refresh) --刷新率與所測屏的分辨率相關
begin
CASE refresh IS
WHEN "01"=>HTOT<=750;
VTOT<=1440;
WHEN "10"=>HTOT<=700;
VTOT<=1102;
WHEN OTHERS =>HTOT<=750;
VTOT<=1200;
END CASE;
END PROCESS;
process(clk) --所產生圖像的rgb選擇
begin
if clk'event AND clk = '1' THEN
CASE rgb_sel IS
WHEN "00000001"=> --white
out_r_e <= out1_r_e;
out_b_e <= out1_b_e;
out_g_e <= out1_g_e;
out_r_o <= out1_r_o;
out_b_o <= out1_b_o;
out_g_o <= out1_g_o;
WHEN "10000001"=> --red
out_r_e <= out1_r_e;
out_b_e <= "00000000";
out_g_e <= "00000000";
out_r_o <= out1_r_o;
out_b_o <= "00000000";
out_g_o <= "00000000";
WHEN "11000001"=> --blue
out_r_e <= "00000000";
out_b_e <= out1_b_e;
out_g_e <= "00000000";
out_r_o <= "00000000";
out_b_o <= out1_b_o;
out_g_o <= "00000000";
WHEN "01000001"=> --green
out_r_e <= "00000000";
out_b_e <= "00000000";
out_g_e <= out1_g_e;
out_r_o <= "00000000";
out_b_o <= "00000000";
out_g_o <= out1_g_o;
WHEN others=> --white
out_r_e <= out1_r_e;
out_b_e <= out1_b_e;
out_g_e <= out1_g_e;
out_r_o <= out1_r_o;
out_b_o <= out1_b_o;
out_g_o <= out1_g_o;
END CASE;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE chose IS
WHEN "001"=>
out1_r_e <= out2_r_e;
out1_b_e <= out2_b_e;
out1_g_e <= out2_g_e;
out1_r_o <= out2_r_o;
out1_b_o <= out2_b_o;
out1_g_o <= out2_g_o;
when others=>
out1_r_e <= "00000000";
out1_b_e <= "00000000";
out1_g_e <= "00000000";
out1_r_o <= "00000000";
out1_b_o <= "00000000";
out1_g_o <= "00000000";
END CASE;
END IF;
END PROCESS;
pixs_out <='1';
de_out <=hb AND vb;
hs_out <=hs;
vs_out <=vs;
datain <=count1;
END rtl;?? 快捷鍵說明
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