|image
clk => rs232_r:U1.inclk
clk => rs232_t:u5.clk
clk => amp:U4.clk
clk => pll:U3.inclk0
txd <= rs232_t:u5.txd
clk_out <= pll:U3.c0
hs_out <= image1:U2.hs_out
de_out <= image1:U2.de_out
vs_out <= image1:U2.vs_out
pixs_out <= image1:U2.pixs_out
trigger <= image1:U2.trigger
panelsel <= amp:U4.panelsel
pu <= amp:U4.pu
pd <= amp:U4.pd
out_r_e[0] <= image1:U2.out_r_e[0]
out_r_e[1] <= image1:U2.out_r_e[1]
out_r_e[2] <= image1:U2.out_r_e[2]
out_r_e[3] <= image1:U2.out_r_e[3]
out_r_e[4] <= image1:U2.out_r_e[4]
out_r_e[5] <= image1:U2.out_r_e[5]
out_r_e[6] <= image1:U2.out_r_e[6]
out_r_e[7] <= image1:U2.out_r_e[7]
out_g_e[0] <= image1:U2.out_g_e[0]
out_g_e[1] <= image1:U2.out_g_e[1]
out_g_e[2] <= image1:U2.out_g_e[2]
out_g_e[3] <= image1:U2.out_g_e[3]
out_g_e[4] <= image1:U2.out_g_e[4]
out_g_e[5] <= image1:U2.out_g_e[5]
out_g_e[6] <= image1:U2.out_g_e[6]
out_g_e[7] <= image1:U2.out_g_e[7]
out_b_e[0] <= image1:U2.out_b_e[0]
out_b_e[1] <= image1:U2.out_b_e[1]
out_b_e[2] <= image1:U2.out_b_e[2]
out_b_e[3] <= image1:U2.out_b_e[3]
out_b_e[4] <= image1:U2.out_b_e[4]
out_b_e[5] <= image1:U2.out_b_e[5]
out_b_e[6] <= image1:U2.out_b_e[6]
out_b_e[7] <= image1:U2.out_b_e[7]
out_r_o[0] <= image1:U2.out_r_o[0]
out_r_o[1] <= image1:U2.out_r_o[1]
out_r_o[2] <= image1:U2.out_r_o[2]
out_r_o[3] <= image1:U2.out_r_o[3]
out_r_o[4] <= image1:U2.out_r_o[4]
out_r_o[5] <= image1:U2.out_r_o[5]
out_r_o[6] <= image1:U2.out_r_o[6]
out_r_o[7] <= image1:U2.out_r_o[7]
out_g_o[0] <= image1:U2.out_g_o[0]
out_g_o[1] <= image1:U2.out_g_o[1]
out_g_o[2] <= image1:U2.out_g_o[2]
out_g_o[3] <= image1:U2.out_g_o[3]
out_g_o[4] <= image1:U2.out_g_o[4]
out_g_o[5] <= image1:U2.out_g_o[5]
out_g_o[6] <= image1:U2.out_g_o[6]
out_g_o[7] <= image1:U2.out_g_o[7]
out_b_o[0] <= image1:U2.out_b_o[0]
out_b_o[1] <= image1:U2.out_b_o[1]
out_b_o[2] <= image1:U2.out_b_o[2]
out_b_o[3] <= image1:U2.out_b_o[3]
out_b_o[4] <= image1:U2.out_b_o[4]
out_b_o[5] <= image1:U2.out_b_o[5]
out_b_o[6] <= image1:U2.out_b_o[6]
out_b_o[7] <= image1:U2.out_b_o[7]


|image|pll:U3
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|image|pll:U3|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|image|amp:U4
clk => amp1[3].CLK
clk => amp1[2].CLK
clk => amp1[1].CLK
clk => amp1[0].CLK
clk => amp2[3].CLK
clk => amp2[2].CLK
clk => amp2[1].CLK
clk => amp2[0].CLK
clk => ctrl.CLK
clk => ctrl31_enable.CLK
clk => count31[26].CLK
clk => count31[25].CLK
clk => count31[24].CLK
clk => count31[23].CLK
clk => count31[22].CLK
clk => count31[21].CLK
clk => count31[20].CLK
clk => count31[19].CLK
clk => count31[18].CLK
clk => count31[17].CLK
clk => count31[16].CLK
clk => count31[15].CLK
clk => count31[14].CLK
clk => count31[13].CLK
clk => count31[12].CLK
clk => count31[11].CLK
clk => count31[10].CLK
clk => count31[9].CLK
clk => count31[8].CLK
clk => count31[7].CLK
clk => count31[6].CLK
clk => count31[5].CLK
clk => count31[4].CLK
clk => count31[3].CLK
clk => count31[2].CLK
clk => count31[1].CLK
clk => count31[0].CLK
clk => ctrl52_enable.CLK
clk => count52[27].CLK
clk => count52[26].CLK
clk => count52[25].CLK
clk => count52[24].CLK
clk => count52[23].CLK
clk => count52[22].CLK
clk => count52[21].CLK
clk => count52[20].CLK
clk => count52[19].CLK
clk => count52[18].CLK
clk => count52[17].CLK
clk => count52[16].CLK
clk => count52[15].CLK
clk => count52[14].CLK
clk => count52[13].CLK
clk => count52[12].CLK
clk => count52[11].CLK
clk => count52[10].CLK
clk => count52[9].CLK
clk => count52[8].CLK
clk => count52[7].CLK
clk => count52[6].CLK
clk => count52[5].CLK
clk => count52[4].CLK
clk => count52[3].CLK
clk => count52[2].CLK
clk => count52[1].CLK
clk => count52[0].CLK
clk => ctrl56_enable.CLK
clk => count56[27].CLK
clk => count56[26].CLK
clk => count56[25].CLK
clk => count56[24].CLK
clk => count56[23].CLK
clk => count56[22].CLK
clk => count56[21].CLK
clk => count56[20].CLK
clk => count56[19].CLK
clk => count56[18].CLK
clk => count56[17].CLK
clk => count56[16].CLK
clk => count56[15].CLK
clk => count56[14].CLK
clk => count56[13].CLK
clk => count56[12].CLK
clk => count56[11].CLK
clk => count56[10].CLK
clk => count56[9].CLK
clk => count56[8].CLK
clk => count56[7].CLK
clk => count56[6].CLK
clk => count56[5].CLK
clk => count56[4].CLK
clk => count56[3].CLK
clk => count56[2].CLK
clk => count56[1].CLK
clk => count56[0].CLK
clk => ctrl58_enable.CLK
clk => count58[27].CLK
clk => count58[26].CLK
clk => count58[25].CLK
clk => count58[24].CLK
clk => count58[23].CLK
clk => count58[22].CLK
clk => count58[21].CLK
clk => count58[20].CLK
clk => count58[19].CLK
clk => count58[18].CLK
clk => count58[17].CLK
clk => count58[16].CLK
clk => count58[15].CLK
clk => count58[14].CLK
clk => count58[13].CLK
clk => count58[12].CLK
clk => count58[11].CLK
clk => count58[10].CLK
clk => count58[9].CLK
clk => count58[8].CLK
clk => count58[7].CLK
clk => count58[6].CLK
clk => count58[5].CLK
clk => count58[4].CLK
clk => count58[3].CLK
clk => count58[2].CLK
clk => count58[1].CLK
clk => count58[0].CLK
clk => ctrl59_enable.CLK
clk => count59[27].CLK
clk => count59[26].CLK
clk => count59[25].CLK
clk => count59[24].CLK
clk => count59[23].CLK
clk => count59[22].CLK
clk => count59[21].CLK
clk => count59[20].CLK
clk => count59[19].CLK
clk => count59[18].CLK
clk => count59[17].CLK
clk => count59[16].CLK
clk => count59[15].CLK
clk => count59[14].CLK
clk => count59[13].CLK
clk => count59[12].CLK
clk => count59[11].CLK
clk => count59[10].CLK
clk => count59[9].CLK
clk => count59[8].CLK
clk => count59[7].CLK
clk => count59[6].CLK
clk => count59[5].CLK
clk => count59[4].CLK
clk => count59[3].CLK
clk => count59[2].CLK
clk => count59[1].CLK
clk => count59[0].CLK
clk => ctrl60_enable.CLK
clk => count60[27].CLK
clk => count60[26].CLK
clk => count60[25].CLK
clk => count60[24].CLK
clk => count60[23].CLK
clk => count60[22].CLK
clk => count60[21].CLK
clk => count60[20].CLK
clk => count60[19].CLK
clk => count60[18].CLK
clk => count60[17].CLK
clk => count60[16].CLK
clk => count60[15].CLK
clk => count60[14].CLK
clk => count60[13].CLK
clk => count60[12].CLK
clk => count60[11].CLK
clk => count60[10].CLK
clk => count60[9].CLK
clk => count60[8].CLK
clk => count60[7].CLK
clk => count60[6].CLK
clk => count60[5].CLK
clk => count60[4].CLK
clk => count60[3].CLK
clk => count60[2].CLK
clk => count60[1].CLK
clk => count60[0].CLK
clk => pu~reg0.CLK
clk => pd~reg0.CLK
clk => count:U1.clkin
clk => panelsel~reg0.CLK
panel[0] => reduce_nor~0.IN6
panel[1] => reduce_nor~0.IN5
panel[2] => reduce_nor~0.IN4
panel[3] => reduce_nor~0.IN3
panel[4] => reduce_nor~0.IN2
panel[5] => reduce_nor~0.IN1
panel[6] => reduce_nor~0.IN0
panel[7] => reduce_nor~0.IN7
amp[0] => reduce_nor~1.IN5
amp[0] => reduce_nor~2.IN5
amp[0] => reduce_nor~3.IN5
amp[0] => reduce_nor~4.IN5
amp[0] => reduce_nor~5.IN5
amp[0] => reduce_nor~6.IN5
amp[0] => reduce_nor~7.IN5
amp[0] => reduce_nor~8.IN5
amp[1] => reduce_nor~1.IN4
amp[1] => reduce_nor~2.IN4
amp[1] => reduce_nor~3.IN4
amp[1] => reduce_nor~4.IN4
amp[1] => reduce_nor~5.IN4
amp[1] => reduce_nor~6.IN4
amp[1] => reduce_nor~7.IN4
amp[1] => reduce_nor~8.IN4
amp[2] => reduce_nor~1.IN3
amp[2] => reduce_nor~2.IN3
amp[2] => reduce_nor~3.IN3
amp[2] => reduce_nor~4.IN3
amp[2] => reduce_nor~5.IN3
amp[2] => reduce_nor~6.IN3
amp[2] => reduce_nor~7.IN3
amp[2] => reduce_nor~8.IN3
amp[3] => reduce_nor~1.IN2
amp[3] => reduce_nor~2.IN2
amp[3] => reduce_nor~3.IN2
amp[3] => reduce_nor~4.IN2
amp[3] => reduce_nor~5.IN2
amp[3] => reduce_nor~6.IN2
amp[3] => reduce_nor~7.IN2
amp[3] => reduce_nor~8.IN2
amp[4] => reduce_nor~1.IN6
amp[4] => reduce_nor~2.IN6
amp[4] => reduce_nor~3.IN6
amp[4] => reduce_nor~4.IN6
amp[4] => reduce_nor~5.IN6
amp[4] => reduce_nor~6.IN6
amp[4] => reduce_nor~7.IN6
amp[4] => reduce_nor~8.IN6
amp[5] => reduce_nor~1.IN1
amp[5] => reduce_nor~2.IN1
amp[5] => reduce_nor~5.IN1
amp[5] => reduce_nor~6.IN1
amp[5] => reduce_nor~7.IN1
amp[5] => reduce_nor~8.IN1
amp[5] => reduce_nor~3.IN1
amp[5] => reduce_nor~4.IN1
amp[6] => reduce_nor~1.IN0
amp[6] => reduce_nor~3.IN0
amp[6] => reduce_nor~5.IN0
amp[6] => reduce_nor~7.IN0
amp[6] => reduce_nor~6.IN0
amp[6] => reduce_nor~8.IN0
amp[6] => reduce_nor~4.IN0
amp[6] => reduce_nor~2.IN0
amp[7] => reduce_nor~1.IN7
amp[7] => reduce_nor~5.IN7
amp[7] => reduce_nor~6.IN7
amp[7] => reduce_nor~7.IN7
amp[7] => reduce_nor~8.IN7
amp[7] => reduce_nor~3.IN7
amp[7] => reduce_nor~4.IN7
amp[7] => reduce_nor~2.IN7
panelsel <= panelsel~reg0.DB_MAX_OUTPUT_PORT_TYPE
pu <= pu~reg0.DB_MAX_OUTPUT_PORT_TYPE
pd <= pd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|amp:U4|count:U1
clkin => count[20].CLK
clkin => count[19].CLK
clkin => count[18].CLK
clkin => count[17].CLK
clkin => count[16].CLK
clkin => count[15].CLK
clkin => count[14].CLK
clkin => count[13].CLK
clkin => count[12].CLK
clkin => count[11].CLK
clkin => count[10].CLK
clkin => count[9].CLK
clkin => count[8].CLK
clkin => count[7].CLK
clkin => count[6].CLK
clkin => count[5].CLK
clkin => count[4].CLK
clkin => count[3].CLK
clkin => count[2].CLK
clkin => count[1].CLK
clkin => count[0].CLK
clkin => clkout~reg0.CLK
clkin => count[21].CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|rs232_t:u5
clk => dataout[6].CLK
clk => dataout[5].CLK
clk => dataout[4].CLK
clk => dataout[3].CLK
clk => dataout[2].CLK
clk => dataout[1].CLK
clk => dataout[0].CLK
clk => send:u2.clk
clk => pll1:u1.inclk0
clk => dataout[7].CLK
ctrl => send:u2.ctrl
datain[0] => dataout[7].DATAIN
datain[1] => dataout[6].DATAIN
datain[2] => dataout[5].DATAIN
datain[3] => dataout[4].DATAIN
datain[4] => dataout[3].DATAIN
datain[5] => dataout[2].DATAIN
datain[6] => dataout[1].DATAIN
datain[7] => dataout[0].DATAIN
txd <= send:u2.dout