PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATAOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
clk0
inclk0
inclk1
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|stratix_pll.inc
1107575584
c:|altera|quartus50|libraries|megafunctions|stratixii_pll.inc
1107575806
c:|altera|quartus50|libraries|megafunctions|cycloneii_pll.inc
1107575944
}
# hierarchies {
pll:U3|altpll:altpll_component
}
# end
# entity
amp
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
amp.vhd
1180956504
4
# storage
db|image.(3).cnf
db|image.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
amp:U4
}
# end
# entity
count
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
count.vhd
1180952608
4
# storage
db|image.(4).cnf
db|image.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
amp:U4|count:U1
}
# end
# entity
rs232_t
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rs232_t.vhd
1180956768
4
# storage
db|image.(5).cnf
db|image.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rs232_t:u5
}
# end
# entity
pll1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
pll1.vhd
1180956548
4
# storage
db|image.(6).cnf
db|image.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rs232_t:u5|pll1:u1
rs232_r:U1|pll1:u1
}
# end
# entity
send
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
send.vhd
1180956646
4
# storage
db|image.(7).cnf
db|image.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rs232_t:u5|send:u2
}
# end
# entity
rs232_r
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rs232_r.vhd
1180952378
4
# storage
db|image.(8).cnf
db|image.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rs232_r:U1
}
# end
# entity
rcv
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rcv.vhd
1180952350
4
# storage
db|image.(9).cnf
db|image.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rs232_r:U1|rcv:u2
}
# end
# entity
image1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
image1.vhd
1188179356
4
# storage
db|image.(10).cnf
db|image.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
image1:U2
}
# end
# entity
shinningblock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
shinningblock.vhd
1178850994
4
# storage
db|image.(11).cnf
db|image.(11).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
image1:U2|shinningblock:U2
}
# end
# complete