{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 21 09:41:18 2008 " "Info: Processing started: Mon Apr 21 09:41:18 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off image -c image " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off image -c image" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "image EP1C6T144C8 " "Info: Selected device EP1C6T144C8 for design \"image\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "pll:U3\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"pll:U3\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll:U3\|altpll:altpll_component\|_clk0 27 20 0 0 " "Info: Implementing clock multiplication of 27, clock division of 20, and phase shift of 0 degrees (0 ps) for pll:U3\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "pll.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/pll.vhd" 86 -1 0 } } { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 123 -1 0 } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C3T144C8 " "Info: Device EP1C3T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 60 " "Info: No exact pin location assignment(s) for 4 pins of 60 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "txd " "Info: Pin txd not assigned to an exact location on the device" {  } { { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "txd" } } } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { txd } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { txd } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "panelsel " "Info: Pin panelsel not assigned to an exact location on the device" {  } { { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "panelsel" } } } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { panelsel } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { panelsel } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pu " "Info: Pin pu not assigned to an exact location on the device" {  } { { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 17 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pu" } } } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { pu } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { pu } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pd " "Info: Pin pd not assigned to an exact location on the device" {  } { { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pd" } } } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { pd } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { pd } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "clk " "Info: Promoted signal \"clk\" to use global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } { 0 "clk" } } } } { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 8 -1 0 } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { clk } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "pll:U3\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"pll:U3\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pll:U3\|altpll:altpll_component\|_clk0" } { 0 "pll:U3\|altpll:altpll_component\|_clk0" } } } } { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 123 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.fld" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rs232_r:U1\|rcv:u2\|clkdiv\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"rs232_r:U1\|rcv:u2\|clkdiv\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_r:U1\|rcv:u2\|clkdiv\[3\] " "Info: Destination \"rs232_r:U1\|rcv:u2\|clkdiv\[3\]\" may be non-global or may not use global clock" {  } { { "rcv.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/rcv.vhd" 33 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_r:U1\|rcv:u2\|reduce_nor~61 " "Info: Destination \"rs232_r:U1\|rcv:u2\|reduce_nor~61\" may be non-global or may not use global clock" {  } {  } 0}  } { { "rcv.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/rcv.vhd" 33 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rs232_r:U1\|pll1:u1\|c0 Global clock " "Info: Automatically promoted signal \"rs232_r:U1\|pll1:u1\|c0\" to use Global clock" {  } { { "pll1.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/pll1.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rs232_t:u5\|send:u2\|clkdiv\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"rs232_t:u5\|send:u2\|clkdiv\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|clkdiv\[3\] " "Info: Destination \"rs232_t:u5\|send:u2\|clkdiv\[3\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 21 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|reduce_nor~59 " "Info: Destination \"rs232_t:u5\|send:u2\|reduce_nor~59\" may be non-global or may not use global clock" {  } {  } 0}  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 21 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkx Global clock " "Info: Automatically promoted some destinations of signal \"clkx\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|clk1x_enable " "Info: Destination \"rs232_t:u5\|send:u2\|clk1x_enable\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 18 -1 0 } }  } 0}  } { { "image.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/image.vhd" 30 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rs232_t:u5\|send:u2\|clk1x_enable Global clock " "Info: Automatically promoted some destinations of signal \"rs232_t:u5\|send:u2\|clk1x_enable\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|no_bits_sent\[3\] " "Info: Destination \"rs232_t:u5\|send:u2\|no_bits_sent\[3\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|no_bits_sent\[2\] " "Info: Destination \"rs232_t:u5\|send:u2\|no_bits_sent\[2\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|no_bits_sent\[1\] " "Info: Destination \"rs232_t:u5\|send:u2\|no_bits_sent\[1\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|no_bits_sent\[0\] " "Info: Destination \"rs232_t:u5\|send:u2\|no_bits_sent\[0\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|clk1x_enable " "Info: Destination \"rs232_t:u5\|send:u2\|clk1x_enable\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232_t:u5\|send:u2\|clkdiv\[0\] " "Info: Destination \"rs232_t:u5\|send:u2\|clkdiv\[0\]\" may be non-global or may not use global clock" {  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 21 -1 0 } }  } 0}  } { { "send.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/send.vhd" 18 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rs232_t:u5\|pll1:u1\|c0 Global clock " "Info: Automatically promoted signal \"rs232_t:u5\|pll1:u1\|c0\" to use Global clock" {  } { { "pll1.vhd" "" { Text "D:/study/畢業(yè)設(shè)計(jì)/韓健程序/cyclic/pll1.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}