{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 0 4 0 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 5 17 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 6 20 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  20 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 21 3 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 21 total pin(s) used --  3 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 26 0 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 26 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll:U3\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll:U3\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "pll.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/pll.vhd" 86 -1 0 } } { "image.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/image.vhd" 123 -1 0 } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.878 ns register register " "Info: Estimated most critical path is register to register delay of 1.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_r:U1\|rcv:u2\|rgb_sel\[3\] 1 REG LAB_X29_Y15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y15; Fanout = 1; REG Node = 'rs232_r:U1\|rcv:u2\|rgb_sel\[3\]'" {  } { { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "" { rs232_r:U1|rcv:u2|rgb_sel[3] } "NODE_NAME" } "" } } { "rcv.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.203 ns) + CELL(0.590 ns) 0.793 ns rs232_r:U1\|rcv:u2\|rgb_sel\[2\]~156 2 COMB LAB_X29_Y15 24 " "Info: 2: + IC(0.203 ns) + CELL(0.590 ns) = 0.793 ns; Loc. = LAB_X29_Y15; Fanout = 24; COMB Node = 'rs232_r:U1\|rcv:u2\|rgb_sel\[2\]~156'" {  } { { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "0.793 ns" { rs232_r:U1|rcv:u2|rgb_sel[3] rs232_r:U1|rcv:u2|rgb_sel[2]~156 } "NODE_NAME" } "" } } { "rcv.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.309 ns) 1.878 ns image1:U2\|out_r_e\[0\] 3 REG LAB_X30_Y15 2 " "Info: 3: + IC(0.776 ns) + CELL(0.309 ns) = 1.878 ns; Loc. = LAB_X30_Y15; Fanout = 2; REG Node = 'image1:U2\|out_r_e\[0\]'" {  } { { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "1.085 ns" { rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_r_e[0] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/image1.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.899 ns 47.87 % " "Info: Total cell delay = 0.899 ns ( 47.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.979 ns 52.13 % " "Info: Total interconnect delay = 0.979 ns ( 52.13 % )" {  } {  } 0}  } { { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "1.878 ns" { rs232_r:U1|rcv:u2|rgb_sel[3] rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_r_e[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Info: Fitter placement operations ending: elapsed time is 00:00:07" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 6 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 6%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: The following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "rxd a permanently enabled " "Info: Pin rxd has a permanently enabled output enable" {  } { { "image.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/image.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rxd" } } } } { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "" { rxd } "NODE_NAME" } "" } } { "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" "" { rxd } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: The following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pixs_out VCC " "Info: Pin pixs_out has VCC driving its datain port" {  } { { "image.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/image.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pixs_out" } } } } { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "" { pixs_out } "NODE_NAME" } "" } } { "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" "" { pixs_out } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "rxd VCC " "Info: Pin rxd has VCC driving its datain port" {  } { { "image.vhd" "" { Text "D:/study/畢業設計/韓健程序/cyclic/image.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rxd" } } } } { "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/畢業設計/韓健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/畢業設計/韓健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/" "" "" { rxd } "NODE_NAME" } "" } } { "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" { Floorplan "D:/study/畢業設計/韓健程序/cyclic/image.fld" "" "" { rxd } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 09:41:41 2008 " "Info: Processing ended: Mon Apr 21 09:41:41 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Info: Elapsed time: 00:00:23" {  } {  } 0}  } {  } 0}