MB1L25 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[3], MB1L23);


--MB1_ram_rom_addr_reg[4] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], !FB5_Q[0], MB1L12, MB1L25);

--MB1L27 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~137
--operation mode is arithmetic

MB1L27 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[4], MB1L25);


--MB1_ram_rom_addr_reg[5] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], !FB5_Q[0], MB1L12, MB1L27);

--MB1L29 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~141
--operation mode is arithmetic

MB1L29 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[5], MB1L27);


--MB1_ram_rom_addr_reg[6] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[6] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7], !FB5_Q[0], MB1L12, MB1L29);

--MB1L31 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]~145
--operation mode is arithmetic

MB1L31 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[6], MB1L29);


--MB1_ram_rom_addr_reg[7] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]
--operation mode is normal

MB1_ram_rom_addr_reg[7] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[7], altera_internal_jtag, !FB5_Q[0], MB1L12, MB1L31);


--MB1_ram_rom_data_reg[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

MB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, LB1_q_b[1], MB1_ram_rom_data_reg[2], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

MB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, LB1_q_b[2], MB1_ram_rom_data_reg[3], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

MB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, LB1_q_b[3], MB1_ram_rom_data_reg[4], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[4] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

MB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, LB1_q_b[4], MB1_ram_rom_data_reg[5], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[5] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

MB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, LB1_q_b[5], MB1_ram_rom_data_reg[6], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[6] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

MB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, LB1_q_b[6], MB1_ram_rom_data_reg[7], MB1L13, VCC, MB1L42);


--MB1_ram_rom_data_reg[7] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

MB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, LB1_q_b[7], altera_internal_jtag, MB1L13, VCC, MB1L42);


--state.reset1 is state.reset1
--operation mode is normal

state.reset1_lut_out = VCC;
state.reset1 = DFFEAS(state.reset1_lut_out, CLK_400HZ, !RES, , , , , , );


--state.func_set is state.func_set
--operation mode is normal

state.func_set_lut_out = state.hold & next_command.func_set;
state.func_set = DFFEAS(state.func_set_lut_out, CLK_400HZ, !RES, , , , , , );


--state.reset2 is state.reset2
--operation mode is normal

state.reset2_lut_out = state.hold & (!next_command.reset2);
state.reset2 = DFFEAS(state.reset2_lut_out, CLK_400HZ, !RES, , , , , , );


--state.reset3 is state.reset3
--operation mode is normal

state.reset3_lut_out = state.hold & next_command.reset3;
state.reset3 = DFFEAS(state.reset3_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L158 is state.display_clear~78
--operation mode is normal

A1L158 = state.reset1 & !state.func_set & !state.reset2 & !state.reset3;


--state.display_on is state.display_on
--operation mode is normal

state.display_on_lut_out = state.hold & next_command.display_on;
state.display_on = DFFEAS(state.display_on_lut_out, CLK_400HZ, !RES, , , , , , );


--state.display_off is state.display_off
--operation mode is normal

state.display_off_lut_out = state.hold & next_command.display_off;
state.display_off = DFFEAS(state.display_off_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L159 is state.display_clear~79
--operation mode is normal

A1L159 = A1L158 & (!state.display_on & !state.display_off);


--state.display_set is state.display_set
--operation mode is normal

state.display_set_lut_out = state.hold & next_command.display_set;
state.display_set = DFFEAS(state.display_set_lut_out, CLK_400HZ, !RES, , , , , , );


--state.toggle_e is state.toggle_e
--operation mode is normal

state.toggle_e_lut_out = A1L140;
state.toggle_e = DFFEAS(state.toggle_e_lut_out, CLK_400HZ, !RES, , , , , , );


--state.hold is state.hold
--operation mode is normal

state.hold_lut_out = state.toggle_e & (!state.hold);
state.hold = DFFEAS(state.hold_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L160 is state.display_clear~80
--operation mode is normal

A1L160 = !state.display_set & !state.toggle_e & !state.hold;


--state.display_clear is state.display_clear
--operation mode is normal

state.display_clear_lut_out = state.hold & next_command.display_clear;
state.display_clear = DFFEAS(state.display_clear_lut_out, CLK_400HZ, !RES, , , , , , );


--state.mode_set is state.mode_set
--operation mode is normal

state.mode_set_lut_out = state.hold & next_command.mode_set;
state.mode_set = DFFEAS(state.mode_set_lut_out, CLK_400HZ, !RES, , , , , , );


--state.return_home is state.return_home
--operation mode is normal

state.return_home_lut_out = state.hold & next_command.return_home;
state.return_home = DFFEAS(state.return_home_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L161 is state.display_clear~81
--operation mode is normal

A1L161 = A1L160 & !state.display_clear & !state.mode_set & !state.return_home;


--CLK_400HZ is CLK_400HZ
--operation mode is normal

CLK_400HZ_lut_out = !RES & (CLK_400HZ $ !A1L96);
CLK_400HZ = DFFEAS(CLK_400HZ_lut_out, CLK, VCC, , , , , , );


--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal

C1_hub_tdo = AMPP_FUNCTION(!A1L5, C1L14, C1L17, C1L20, C1L21, !HB1_state[8]);


--HB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal

HB1_state[4] = AMPP_FUNCTION(A1L5, HB1_state[7], HB1_state[3], HB1_state[4], VCC, A1L7);


--HB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal

HB1_state[3] = AMPP_FUNCTION(A1L5, HB1_state[2], A1L7, VCC);


--FB7_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

FB7_Q[2] = AMPP_FUNCTION(A1L5, FB3_Q[2], C1_CLRN_SIGNAL, C1L9);


--FB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

FB3_Q[2] = AMPP_FUNCTION(A1L5, J1L4, MB1_ir_loaded_address_reg[1], FB3_Q[3], C1L22, C1_CLRN_SIGNAL, HB1_state[4], FB3L4);


--C1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL
--operation mode is normal

C1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, HB1_state[1], FB1_Q[0], VCC);


--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, HB1_state[4], HB1_state[8], VCC);


--C1L33 is sld_hub:sld_hub_inst|node_ena~42
--operation mode is normal

C1L33 = AMPP_FUNCTION(FB8_Q[0], FB2_Q[0]);


--FB9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal

FB9_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, FB3_Q[8], VCC, C1L23);


--JB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2]
--operation mode is normal

JB1_dffe1a[2] = AMPP_FUNCTION(A1L5, FB3_Q[2], C1L31, FB3_Q[1], FB3_Q[3], C1_CLRN_SIGNAL, C1L5);


--C1L24 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~124
--operation mode is normal

C1L24 = AMPP_FUNCTION(FB2_Q[0], FB9_Q[0], JB1_dffe1a[2]);


--C1L25 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125
--operation mode is normal

C1L25 = AMPP_FUNCTION(HB1_state[5], C1_OK_TO_UPDATE_IR_Q, C1L33, C1L24);


--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0
--operation mode is normal

C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, C1L6, C1L7, M5_dffs[1], M5_dffs[0], HB1_state[0], HB1_state[12]);


--C1L31 is sld_hub:sld_hub_inst|jtag_debug_mode~2
--operation mode is normal

C1L31 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);