library IEEE;
use IEEE.std_logic_1164.all;
entity seg7_1a is
   port(
      aa:in STD_LOGIC_VECTOR(3 downto 0);
      bb:out STD_LOGIC_VECTOR(6 downto 0);
aaa:out std_logic_vector(3 downto 0);
      cat:out std_logic_vector(5 downto 0)
);
end seg7_1a;
architecture seg7_1a_arch of seg7_1a is
  component seg7_1
port(a:in STD_LOGIC_VECTOR(3 downto 0);
    b:out STD_LOGIC_VECTOR(6 downto 0)
);
end component;
begin
u1:seg7_1 port map(a=>aa,b=>bb);
aaa<=aa;
  cat<="111110";
end seg7_1a_arch;