------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    15:37:59 12/04/2007 -- Design Name: -- Module Name:    reverse - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity revise_motor is port(
--control
reset, clk:in std_logic;
--sensor
sensor_l, sensor_m, sensor_r: in std_logic_vector(1 downto 0);
--input from FPGA
dir, pwm: in std_logic_vector(1 downto 0);
--output
dira, dirb: out std_logic_vector(1 downto 0);
--driver motor
dirdriver: in std_logic_vector(1 downto 0);
diradriver, dirbdriver: out std_logic_vector(1 downto 0));
end revise_motor;

architecture Behavioral of revise_motor is
component revise_fsm 
							port(
							--control
							reset, clk:in std_logic;
							--sensor
							sensor_l, sensor_m, sensor_r: in std_logic;
							--input from FPGA
							dir, pwm: in std_logic;
							--output
							dira, dirb: out std_logic);
end component;

begin
	U1: for i in 0 to 1 generate
	begin
		revise_motor: revise_fsm port map(reset, clk, sensor_l(i), sensor_m(i), sensor_r(i),
											dir(i), pwm(i), dira(i), dirb(i));
	end generate;
	process(reset ,clk)
	begin
		if(reset = '0')then
			diradriver <= "00";
			dirbdriver <= "00";
		elsif(rising_edge(clk))then
			if(dirdriver(0) = dirdriver(1))then
				diradriver(0) <= dirdriver(0);
				dirbdriver(0) <= not dirdriver(0);
				diradriver(1) <= dirdriver(0);
				dirbdriver(1) <= not dirdriver(0);
			else
				diradriver <= "00";
				dirbdriver <= "00";
			end if;
		end if;
	end process;
end Behavioral;

---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity revise_fsm is port(
--control
reset, clk:in std_logic;
--sensor
sensor_l, sensor_m, sensor_r: in std_logic;
--input from FPGA
dir, pwm: in std_logic;
--output
dira, dirb: out std_logic);
end revise_fsm;

architecture Behavioral of revise_fsm is
--s0:stop s1:clockwise s2: anticlockwise, s3: special state
type states is(s0, s1, s2, s3, s4, s5, s6);
--attribute enum_encoding: string;
--attribute enum_encoding of states: type is "000 001 010 011 100 101 110 111";
signal next_state, current_state: states;
begin
process(reset, clk)
begin	
	if(reset = '0')then
		current_state <= s0;		
	elsif(rising_edge(clk))then
		current_state <= next_state;
	end if;
end process;

process(current_state, dir, pwm, sensor_l, sensor_m, sensor_r)
begin
	case current_state is
		when s0 =>		--stop state	
			if(sensor_l = '1' and sensor_r = '1' and sensor_m = '1')then
				if(dir = '1')then --clockwise
					next_state <= s1;
				elsif(dir = '0')then --anticlockwise
					next_state <= s2;
				end if;
			elsif(sensor_l = '0' and dir = '0')then --left position constraint
				next_state <= s0;
			elsif(sensor_l = '0' and dir = '1')then
				next_state <= s1;
			elsif(sensor_r = '0' and dir = '1')then -- right position constraint
				next_state <= s0;
			elsif(sensor_r = '0' and dir = '0')then
				next_state <= s2;
			elsif(sensor_m = '0' and pwm = '1')then -- middle positon constraint
				next_state <= s0;
			elsif(sensor_m = '0' and pwm = '0')then
				next_state <= s3;
			else
				next_state <= s0;
			end if;				
		when s1 =>		--clockwise state, dir = '1'
			if(sensor_l = '0' and dir = '0')then --left position constraint
				next_state <= s0;
			elsif(sensor_l = '0' and dir = '1')then
				next_state <= s1;
			elsif(dir = '1' and sensor_r = '0')then --right position constraint
				next_state <= s0;
			elsif(dir = '0' and sensor_r = '0')then
				next_state <= s2;
			elsif(sensor_m = '0' and pwm = '1')then
				next_state <= s0;
			elsif(sensor_m = '0' and pwm = '0')then
				next_state <= s3;
			elsif(sensor_l = '1' and sensor_r = '1' and sensor_m = '1' and dir = '0')then
				next_state <= s2;
			else
				next_state <= s1;
			end if;			
		when s2 =>		--anticlockwise state, dir = '0'
			if(sensor_m = '0')then --middle position constraint
				next_state <= s5;	
			elsif(dir = '0' and sensor_l = '0')then --left position constraint
				next_state <= s0;
			elsif(dir = '1' and sensor_l = '0')then
				next_state <= s1;
			elsif(sensor_r = '0' and dir = '0')then
				next_state <= s2;
			elsif(sensor_r = '0' and dir = '1')then
				next_state <= s0;
			elsif(sensor_l = '1' and sensor_r = '1' and sensor_m = '1' and dir = '1')then
				next_state <= s1;
			else
				next_state <= s2;
			end if;			
		when s3 =>
			if(pwm = '1')then
				next_state <= s4;
			else
				next_state <= s3;
			end if;
		when s4 =>
			if(sensor_l = '0' or sensor_r = '0')then
				next_state <= s0;
			elsif(sensor_r = '1' and dir = '0' and sensor_m = '1')then----------
				next_state <= s2;
			else
				next_state <= s4;
			end if;
		when s5 =>
			if(sensor_m = '1')then
				next_state <= s6;
			else
				next_state <= s5;
			end if;			
		when s6 =>
			if(pwm = '0' and dir = '1')then
				next_state <= s1;
			elsif(pwm = '0' and dir = '0')then
				next_state <= s2;
			else
				next_state <= s6;
			end if;
		when others =>
			next_state <= s0;
	end case;
end process;
--output
process(clk, current_state)
begin
	if(rising_edge(clk))then
		case current_state is
			when s0 =>
				dira <= '0';
				dirb <= '0';		
			when s1 =>
				dira <= dir;
				dirb <= not dir;
			when s2 =>
				dira <= dir;
				dirb <= not dir;
			when s3 =>
				dira <= '0';
				dirb <= '0';
			when s4 =>
				dira <= dir;
				dirb <= not dir;
			when s5 =>
				dira <= dir;
				dirb <= not dir;
			when s6 =>
				dira <= '0';
				dirb <= '0';
			when others =>
				dira <= '0';
				dirb <= '0';	
		end case;
	end if;
end process;
		
end Behavioral;