--------------------------------------------------------- Design Name : serial_crc_ccitt-- File Name   : serial_crc.vhd-- Function    : CCITT Serial CRC-- Coder       : Deepak Kumar Tala (Verilog)-- Translator  : Alexander H Pham (VHDL)-------------------------------------------------------library ieee;    use ieee.std_logic_1164.all;entity serial_crc_ccitt is    port (        clk     :in  std_logic;        reset   :in  std_logic;        enable  :in  std_logic;        init    :in  std_logic;        data_in :in  std_logic;        crc_out :out std_logic_vector (15 downto 0)    );end entity;architecture rtl of serial_crc_ccitt is    signal lfsr  :std_logic_vector (15 downto 0);begin    -- Logic to CRC Calculation    process (clk) begin        if (rising_edge(clk)) then            if (reset = '1') then                lfsr <= (others=>'1');            elsif (enable = '1') then                if (init = '1') then                    lfsr <=  (others=>'1');                else                    lfsr(0)  <= data_in xor lfsr(15);                    lfsr(1)  <= lfsr(0);                    lfsr(2)  <= lfsr(1);                    lfsr(3)  <= lfsr(2);                    lfsr(4)  <= lfsr(3);                    lfsr(5)  <= lfsr(4) xor data_in xor lfsr(15);                    lfsr(6)  <= lfsr(5);                    lfsr(7)  <= lfsr(6);                    lfsr(8)  <= lfsr(7);                    lfsr(9)  <= lfsr(8);                    lfsr(10) <= lfsr(9);                    lfsr(11) <= lfsr(10);                    lfsr(12) <= lfsr(11) xor data_in xor lfsr(15);                    lfsr(13) <= lfsr(12);                    lfsr(14) <= lfsr(13);                end if;            end if;        end if;    end process;    crc_out <= lfsr;end architecture;