HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	altshift.tdf
	{
		altshift [DEPTH=0,WIDTH=4,USE_LPM_FOR_AHDL_OPERATORS] []
		{
			7 [DEPTH=0,WIDTH=12,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,data11,data10,data9,data8,data7,data6,data5,data4,data3,data2,data1,data0];
			4 [DEPTH=0,WIDTH=1,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,data0];
			3 [DEPTH=0,WIDTH=5,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result4,result3,result2,result1,result0,data4,data3,data2,data1,data0];
		}
	}
	addcore.tdf
	{
		addcore [DEVICE_FAMILY,CARRY_CHAIN_LENGTH,CARRY_CHAIN,CONSTANT_CIN,width,USE_LPM_FOR_AHDL_OPERATORS] [addcore.inc,aglobal.inc]
		{
			6 [DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,CONSTANT_CIN=0,width=12,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,dataa11,dataa10,dataa9,dataa8,dataa7,dataa6,dataa5,dataa4,dataa3,dataa2,dataa1,dataa0,datab11,datab10,datab9,datab8,datab7,datab6,datab5,datab4,datab3,datab2,datab1,datab0,cin];
			2 [DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,CONSTANT_CIN=0,width=5,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result4,result3,result2,result1,result0,dataa4,dataa3,dataa2,dataa1,dataa0,datab4,datab3,datab2,datab1,datab0,cin];
		}
	}
	lpm_add_sub.tdf
	{
		lpm_add_sub [STYLE,DEVICE_FAMILY,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=NO,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_add_sub.inc,addcore.inc,look_add.inc,bypassff.inc,altshift.inc,aglobal.inc]
		{
			5 [STYLE=NORMAL,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=YES,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH=12,USE_LPM_FOR_AHDL_OPERATORS=OFF] [RESULT11,RESULT10,RESULT9,RESULT8,RESULT7,RESULT6,RESULT5,RESULT4,RESULT3,RESULT2,RESULT1,RESULT0,CIN,DATAB11,DATAB10,DATAB9,DATAB8,DATAB7,DATAB6,DATAB5,DATAB4,DATAB3,DATAB2,DATAB1,DATAB0,DATAA11,DATAA10,DATAA9,DATAA8,DATAA7,DATAA6,DATAA5,DATAA4,DATAA3,DATAA2,DATAA1,DATAA0];
			1 [STYLE=NORMAL,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=YES,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH=5,USE_LPM_FOR_AHDL_OPERATORS=OFF] [RESULT4,RESULT3,RESULT2,RESULT1,RESULT0,CIN,DATAB4,DATAB3,DATAB2,DATAB1,DATAB0,DATAA4,DATAA3,DATAA2,DATAA1,DATAA0];
		}
	}
	sramcontroller.vhd
	{
		sramcontroller [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	sramcontroller::(0,0):(0): sramcontroller.vhd
	{
		lpm_add_sub:1:(30,2):(128): lpm_add_sub.tdf
		{
			addcore:2:(212,4):(49,adder): addcore.tdf;
			altshift:3:(222,2):(71,result_ext_latency_ffs): altshift.tdf;
			altshift:4:(224,2):(87,carry_ext_latency_ffs): altshift.tdf;
			altshift:4:(226,2):(95,oflow_ext_latency_ffs): altshift.tdf;
		}
		lpm_add_sub:5:(56,5):(613): lpm_add_sub.tdf
		{
			addcore:6:(212,4):(70,adder): addcore.tdf;
			altshift:7:(222,2):(113,result_ext_latency_ffs): altshift.tdf;
			altshift:4:(224,2):(143,carry_ext_latency_ffs): altshift.tdf;
			altshift:4:(226,2):(151,oflow_ext_latency_ffs): altshift.tdf;
		}
	}
}