library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity tribuffer is
port
(oe:in std_logic;
datain:in std_logic_vector(7 downto 0);
dataout:out std_logic_vector(7 downto 0)
);
end;
-------------------------------
architecture TriState of tribuffer is
begin
process(oe,datain)
begin
if oe='0'then
dataout<="ZZZZZZZZ";
else
dataout<=datain;
end if;
end process;
end TriState;