?? main.c
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/***************************************************************/
/*PROJECT : AT91SAM926X nor flash programer */
/*company : HongKong Baite(Group) Electronic Co.,Ltd */
/* AUTHOR : 張驛風 */
/* DATE: 2007年6月6日 */
/***************************************************************/
/*
Ver1.00 20070607 can init smc success.
Ver1.01 20070607 can read flash .
Ver1.01 20070607 can write flash bank 2 , can erase bank 2.
Ver1.02 20070608 port to ads1.2 ok. set ro_base as:0x200000 , rw_base as: 0x300000
*/
#include "project.h"
#include "flash.h"
#include "type.h"
#define AT91C_RTT_PRESCAL_1_SECOND 0x8000
/* prototypes */
//*--------------------------------------------------------------------------------------
//* Function Name : AT91F_Init_RTT
//* Object : Initialize RTT
//*--------------------------------------------------------------------------------------*/
void AT91F_Init_RTT(void){
AT91C_BASE_RTTC->RTTC_RTMR = (AT91C_RTT_PRESCAL_1_SECOND & AT91C_RTTC_RTPRES );
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_Printk
//* \brief This function is used to send a string through the DBGU channel
//* (Very low level debugging)
//*----------------------------------------------------------------------------
void AT91F_DBGU_Printk( char *buffer) // \arg pointer to a string ending by \0
{
while(*buffer != '\0') {
while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
}
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_Init
//* \brief NandFlash init
//*----------------------------------------------------------------------------
void AT91F_DBGU_Init (void)
{
// Configure DBGU
AT91F_US_ResetRx((AT91PS_USART)AT91C_BASE_DBGU);
AT91F_US_Configure(
(AT91PS_USART)AT91C_BASE_DBGU, // DBGU base address
AT91B_MASTER_CLOCK, // 100 MHz
AT91C_US_ASYNC_MODE, // mode Register to be programmed
AT91B_DBGU_BAUD_RATE, // baudrate to be programmed
0 // timeguard to be programmed
);
// Open PIO for DBGU
AT91F_DBGU_CfgPIO();
// Enable Transmitter
AT91F_US_EnableTx((AT91PS_USART)AT91C_BASE_DBGU);
AT91F_US_EnableRx((AT91PS_USART)AT91C_BASE_DBGU);
}
//*--------------------------------------------------------------------------------------
//* Function Name : AT91F_InitSdram
//* Object : Initialize the SDRAM
//* Input Parameters :
//* Output Parameters :
//*--------------------------------------------------------------------------------------
void AT91F_InitSDRAM32 (void)
{
unsigned int i;
AT91PS_SDRAMC psdrc = AT91C_BASE_SDRAMC;
AT91F_EBI_EnableSDRAMC(AT91C_BASE_CCFG);
// Configure PIOs
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOC, // PIO controller base address
((unsigned int) AT91C_PC21_D21 ) |
((unsigned int) AT91C_PC18_D18 ) |
((unsigned int) AT91C_PC30_D30 ) |
((unsigned int) AT91C_PC26_D26 ) |
((unsigned int) AT91C_PC20_D20 ) |
((unsigned int) AT91C_PC22_D22 ) |
((unsigned int) AT91C_PC19_D19 ) |
((unsigned int) AT91C_PC25_D25 ) |
((unsigned int) AT91C_PC28_D28 ) |
((unsigned int) AT91C_PC23_D23 ) |
((unsigned int) AT91C_PC16_D16 ) |
((unsigned int) AT91C_PC31_D31 ) |
((unsigned int) AT91C_PC27_D27 ) |
((unsigned int) AT91C_PC29_D29 ) |
((unsigned int) AT91C_PC24_D24 ) |
((unsigned int) AT91C_PC17_D17 ), // Peripheral A
0); // Peripheral B
/*CFG 100 */
psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 |
AT91C_SDRAMC_NR_13 |
AT91C_SDRAMC_CAS_3 |
AT91C_SDRAMC_NB_4_BANKS |
AT91C_SDRAMC_DBW_32_BITS |
AT91C_SDRAMC_TWR_3 |
AT91C_SDRAMC_TRC_7 |
AT91C_SDRAMC_TRP_3 |
AT91C_SDRAMC_TRCD_3 |
AT91C_SDRAMC_TRAS_6 |
AT91C_SDRAMC_TXSR_15 ;
for (i =0; i< 1000;i++);
#if 0
psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
*AT91B_SDRAM_BASE = 0x00000000; // Perform PRCHG
for (i =0; i< 10000;i++);
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
*(AT91B_SDRAM_BASE+4) = 0x00000001; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
*(AT91B_SDRAM_BASE+8) = 0x00000002; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
*(AT91B_SDRAM_BASE+0xc) = 0x00000003; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
*(AT91B_SDRAM_BASE+0x10) = 0x00000004; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
*(AT91B_SDRAM_BASE+0x14) = 0x00000005; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
*(AT91B_SDRAM_BASE+0x18) = 0x00000006; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
*(AT91B_SDRAM_BASE+0x1c) = 0x00000007; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
*(AT91B_SDRAM_BASE+0x20) = 0x00000008; // Perform CBR
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
*(AT91B_SDRAM_BASE+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
psdrc->SDRAMC_TR = (AT91B_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
// (F : system clock freq. MHz
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
*AT91B_SDRAM_BASE = 0x00000000; // Perform Normal mode
#endif
#if 1
psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
*AT91B_SDRAM_BASE = 0x00000000; // Perform PRCHG
for (i =0; i< 10000;i++);
psdrc->SDRAMC_MR = 0x00000004; // Set 1st CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 3 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 4 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 5 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 6 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 7 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
psdrc->SDRAMC_MR = 0x00000004; // Set 8 CBR
*(AT91B_SDRAM_BASE) = 0x00000000; // Perform CBR
#if 1
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
*(AT91B_SDRAM_BASE + 0x0) = 0; // Perform LMR burst=1, lat=2
#endif
psdrc->SDRAMC_TR = 781; // Set Refresh Timer 781 for 100MHz
// (F : system clock freq. MHz
psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
*AT91B_SDRAM_BASE = 0x00000000; // Perform Normal mode
#endif
}
char *Date = __DATE__;
char *Time = __TIME__;
char *Ver = "Ver1.0.2";
#define putchar(x) {\
while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));\
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, x);\
};
#define printf(x) AT91F_DBGU_Printk(x);
//*----------------------------------------------------------------------------
//* Function Name : main
//* Object : Main function
//* Input Parameters : none
//* Output Parameters : True
//*----------------------------------------------------------------------------*/
#define putchar(x) {\
while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));\
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, x);\
};
void sendhex (int hex) {
while( !AT91F_US_TxReady( (AT91PS_USART) AT91C_BASE_DBGU) );
if (hex > 9){
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU,'A' + (hex - 10));
}else {
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU,'0' + hex);
}
}
/***********************************************************************/
/*名稱:sendhexstr */
/*功能:發送hex字符串 */
/*入口參數:no */
/*出口參數:1 正確提供，２ ID不正確 0失敗 */
/***********************************************************************/
void sendhexstr32(long int Temp){
putchar('0');
putchar('x');
// sendhex((Temp>>32)&0x0f);
sendhex((Temp>>28)&0x0f);
sendhex((Temp>>24)&0x0f);
sendhex((Temp>>20)&0x0f);
sendhex((Temp>>16)&0x0f);
sendhex((Temp>>12)&0x0f);
sendhex((Temp>>8)&0x0f);
sendhex((Temp>>4)&0x0f);
sendhex(Temp&0x0f);
}
void sendhexstr16(unsigned int Temp){
putchar('0');
putchar('x');
sendhex((Temp>>12)&0x0f);
sendhex((Temp>>8)&0x0f);
sendhex((Temp>>4)&0x0f);
sendhex(Temp&0x0f);
}
void sendhexstr8(unsigned char Temp){
//putchar('0');
//putchar('x');
sendhex((Temp>>4)&0x0f);
sendhex((Temp)&0x0f);
}
void testSdram(void){
unsigned int i,j;
printf("\r\n");
j = 0;
for(i=0x20000000;i<0x20000000 + 8 * 1024 * 1024;i+=4){
*((unsigned int *) i) = j ++;
}
j = 0;
for(i=0x20000000;i<0x20000000 + 8 * 1024 * 1024;i+=4){
if(*((unsigned int *) i) != j++){
printf("test sdram fail.\r\n");
sendhexstr32(i);
printf(" = ");
sendhexstr32(*((unsigned int *) i));
printf(" = ");
sendhexstr32(j-1);
printf("\r\n");
//goto end;
}
}
printf("test sdram ok.\r\n");
//end:;
}
extern int AT91F_SDRAM_Test (void);
int main(void){
AT91F_DBGU_Init();
AT91F_InitSDRAM32();
printf("---------------------------------------------------");
AT91F_DBGU_Printk("\r\n9260 SDRAM INIT.\r\n");
AT91F_DBGU_Printk("ver1.02");
AT91F_DBGU_Printk("\r\n");
printf("---------------------------------------------------\r\n");
while(1){
unsigned int ch,status;
status = AT91F_US_RxReady((AT91PS_USART)AT91C_BASE_DBGU);
if(status){
ch = AT91F_US_GetChar((AT91PS_USART)AT91C_BASE_DBGU);
while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, ch);
printf("\r\n");
switch(ch){
case 't':
case 'T':{
testSdram();
break;
}
case 's':{
//AT91F_SDRAM_Test();
break;
}
}
}
}
}
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