# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		stop_watch_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:15:48  APRIL 14, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name BDF_FILE stop_watch.bdf
set_global_assignment -name BSF_FILE bcdcnt.bsf
set_global_assignment -name VERILOG_FILE bcdcnt.v
set_global_assignment -name BSF_FILE button.bsf
set_global_assignment -name VERILOG_FILE button.v
set_global_assignment -name BSF_FILE clkdiv5k.bsf
set_global_assignment -name VERILOG_FILE clkdiv5k.v
set_global_assignment -name BSF_FILE clkdiv10K_to_1K.bsf
set_global_assignment -name VERILOG_FILE clkdiv10K_to_1K.v
set_global_assignment -name BSF_FILE clkdiv100.bsf
set_global_assignment -name VERILOG_FILE clkdiv100.v
set_global_assignment -name BSF_FILE p7seg.bsf
set_global_assignment -name VERILOG_FILE p7seg.v
set_global_assignment -name VECTOR_WAVEFORM_FILE stop_watch.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE tt.vwf
set_global_assignment -name CDF_FILE stop_watch.cdf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_141 -to bin_dsec[0]
set_location_assignment PIN_158 -to bin_dsec[1]
set_location_assignment PIN_159 -to bin_dsec[2]
set_location_assignment PIN_160 -to bin_dsec[3]
set_location_assignment PIN_137 -to bin_sec[0]
set_location_assignment PIN_138 -to bin_sec[1]
set_location_assignment PIN_139 -to bin_sec[2]
set_location_assignment PIN_140 -to bin_sec[3]
set_location_assignment PIN_17 -to bin_secd[0]
set_location_assignment PIN_18 -to bin_secd[1]
set_location_assignment PIN_19 -to bin_secd[2]
set_location_assignment PIN_20 -to bin_secd[3]
set_location_assignment PIN_13 -to bin_secm[0]
set_location_assignment PIN_14 -to bin_secm[1]
set_location_assignment PIN_15 -to bin_secm[2]
set_location_assignment PIN_16 -to bin_secm[3]
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_132 -to clrn
set_location_assignment PIN_168 -to cn
set_location_assignment PIN_128 -to startstopn

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY stop_watch

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name SIMULATION_COVERAGE OFF
set_global_assignment -name VECTOR_INPUT_SOURCE stop_watch.vwf