;     -- Total 3-input functions    ; 2       ;
;     -- Total 2-input functions    ; 21      ;
;     -- Total 1-input functions    ; 26      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 53      ;
; Total logic cells in carry chains ; 27      ;
; I/O pins                          ; 49      ;
; Maximum fan-out node              ; clrn    ;
; Maximum fan-out                   ; 45      ;
; Total fan-out                     ; 512     ;
; Average fan-out                   ; 2.75    ;
+-----------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                       ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------+
; Compilation Hierarchy Node  ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------+
; |stop_watch                 ; 137 (2)     ; 53           ; 0           ; 49   ; 0            ; 84 (1)       ; 32 (1)            ; 21 (0)           ; 27 (0)          ; |stop_watch                        ;
;    |bcdcnt:inst28|          ; 27 (27)     ; 17           ; 0           ; 0    ; 0            ; 10 (10)      ; 8 (8)             ; 9 (9)            ; 0 (0)           ; |stop_watch|bcdcnt:inst28          ;
;    |button:inst|            ; 26 (26)     ; 8            ; 0           ; 0    ; 0            ; 18 (18)      ; 7 (7)             ; 1 (1)            ; 7 (7)           ; |stop_watch|button:inst            ;
;    |clkdiv100:inst29|       ; 17 (17)     ; 8            ; 0           ; 0    ; 0            ; 9 (9)        ; 5 (5)             ; 3 (3)            ; 7 (7)           ; |stop_watch|clkdiv100:inst29       ;
;    |clkdiv10K_to_1K:inst27| ; 6 (6)       ; 5            ; 0           ; 0    ; 0            ; 1 (1)        ; 2 (2)             ; 3 (3)            ; 0 (0)           ; |stop_watch|clkdiv10K_to_1K:inst27 ;
;    |clkdiv5k:inst1|         ; 31 (31)     ; 14           ; 0           ; 0    ; 0            ; 17 (17)      ; 9 (9)             ; 5 (5)            ; 13 (13)         ; |stop_watch|clkdiv5k:inst1         ;
;    |p7seg:inst23|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |stop_watch|p7seg:inst23           ;
;    |p7seg:inst24|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |stop_watch|p7seg:inst24           ;
;    |p7seg:inst25|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |stop_watch|p7seg:inst25           ;
;    |p7seg:inst26|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |stop_watch|p7seg:inst26           ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 53    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 41    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in e:/stop_watch/stop_watch.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Apr 14 19:32:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stop_watch -c stop_watch
Info: Found 1 design units, including 1 entities, in source file stop_watch.bdf
    Info: Found entity 1: stop_watch
Info: Found 1 design units, including 1 entities, in source file bcdcnt.v
    Info: Found entity 1: bcdcnt
Info: Found 1 design units, including 1 entities, in source file button.v
    Info: Found entity 1: button
Warning: Verilog HDL warning at clkdiv5k.v(4): using specified range for net, port, or variable "count" that was previously declared without a range specification
Info: Found 1 design units, including 1 entities, in source file clkdiv5k.v
    Info: Found entity 1: clkdiv5k
Warning: Verilog HDL warning at clkdiv10K_to_1K.v(4): using specified range for net, port, or variable "count" that was previously declared without a range specification
Info: Found 1 design units, including 1 entities, in source file clkdiv10K_to_1K.v
    Info: Found entity 1: clkdiv10K_to_1K
Warning: Verilog HDL warning at clkdiv100.v(4): using specified range for net, port, or variable "count" that was previously declared without a range specification
Info: Found 1 design units, including 1 entities, in source file clkdiv100.v
    Info: Found entity 1: clkdiv100
Info: Found 1 design units, including 1 entities, in source file p7seg.v
    Info: Found entity 1: p7seg
Info: Elaborating entity "stop_watch" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst7" overlaps another block or symbol
Warning: Block or symbol "p7seg" of instance "inst23" overlaps another block or symbol
Warning: Block or symbol "p7seg" of instance "inst25" overlaps another block or symbol
Info: Elaborating entity "clkdiv100" for hierarchy "clkdiv100:inst29"
Warning: Verilog HDL assignment warning at clkdiv100.v(8): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at clkdiv100.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv100.v(12): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at clkdiv100.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv100.v(17): truncated value with size 32 to match size of target (7)
Info: Elaborating entity "clkdiv5k" for hierarchy "clkdiv5k:inst1"
Warning: Verilog HDL assignment warning at clkdiv5k.v(8): truncated value with size 32 to match size of target (13)
Warning: Verilog HDL assignment warning at clkdiv5k.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv5k.v(12): truncated value with size 32 to match size of target (13)
Warning: Verilog HDL assignment warning at clkdiv5k.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv5k.v(17): truncated value with size 32 to match size of target (13)
Info: Elaborating entity "button" for hierarchy "button:inst"
Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)
Info: Elaborating entity "clkdiv10K_to_1K" for hierarchy "clkdiv10K_to_1K:inst27"
Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(8): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(12): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(17): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "bcdcnt" for hierarchy "bcdcnt:inst28"
Warning: Verilog HDL assignment warning at bcdcnt.v(11): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(12): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(13): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(14): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(20): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(23): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(26): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(29): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(30): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at bcdcnt.v(32): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(34): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(36): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(40): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at bcdcnt.v(41): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "p7seg" for hierarchy "p7seg:inst23"
Info: Duplicate registers merged to single register
    Info: Duplicate register "button:inst|enable~reg0" merged to single register "button:inst|signal", power-up level changed
Info: Implemented 186 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 46 output pins
    Info: Implemented 137 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings
    Info: Processing ended: Mon Apr 14 19:32:11 2008
    Info: Elapsed time: 00:00:03