?? dds.map.rpt
字號:
; altqpram.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_hq21.tdf ; yes ; Auto-Generated Megafunction ; C:/Documents and Settings/Administrator/桌面/psk_mc/db/altsyncram_hq21.tdf ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 43 ;
; -- Combinational with no register ; 9 ;
; -- Register only ; 9 ;
; -- Combinational with a register ; 25 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 4 ;
; -- 3 input functions ; 2 ;
; -- 2 input functions ; 20 ;
; -- 1 input functions ; 7 ;
; -- 0 input functions ; 1 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 29 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 8 ;
; -- asynchronous clear/load mode ; 5 ;
; ; ;
; Total registers ; 34 ;
; Total logic cells in carry chains ; 16 ;
; I/O pins ; 21 ;
; Total memory bits ; 1024 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 36 ;
; Total fan-out ; 219 ;
; Average fan-out ; 3.04 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
; |DDS ; 43 (1) ; 34 ; 1024 ; 0 ; 21 ; 0 ; 9 (1) ; 9 (0) ; 25 (0) ; 16 (0) ; 0 (0) ; |DDS ;
; |DDS1:u1| ; 16 (11) ; 15 ; 1024 ; 0 ; 0 ; 0 ; 1 (1) ; 4 (0) ; 11 (10) ; 8 (8) ; 0 (0) ; |DDS|DDS1:u1 ;
; |REG7B:u5| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS|DDS1:u1|REG7B:u5 ;
; |sin_rom:u3| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|DDS1:u1|sin_rom:u3 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component ;
; |altsyncram_hq21:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated ;
; |PL_DPSK2:u2| ; 17 (17) ; 11 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 2 (2) ; 9 (9) ; 8 (8) ; 0 (0) ; |DDS|PL_DPSK2:u2 ;
; |fangbo:u3| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS|fangbo:u3 ;
; |ps7:u0| ; 6 (6) ; 5 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 4 (4) ; 0 (0) ; 0 (0) ; |DDS|ps7:u0 ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 128 ; 8 ; -- ; -- ; 1024 ; sin7.mif ;
+----------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 34 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 8 ;
; Number of registers using Asynchronous Clear ; 4 ;
; Number of registers using Asynchronous Load ; 1 ;
; Number of registers using Clock Enable ; 2 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; ps7:u0|c3 ; 3 ;
; ps7:u0|c0 ; 2 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DDS|PL_DPSK2:u2|q[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+------------------------------------------+
; Source assignments for ps7:u0 ;
+----------------+-------+------+----------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low ; - ; count[0] ;
; POWER_UP_LEVEL ; Low ; - ; count[1] ;
; POWER_UP_LEVEL ; Low ; - ; count[2] ;
; POWER_UP_LEVEL ; Low ; - ; count[3] ;
; POWER_UP_LEVEL ; Low ; - ; count[4] ;
; POWER_UP_LEVEL ; Low ; - ; count[5] ;
; POWER_UP_LEVEL ; Low ; - ; count[6] ;
; POWER_UP_LEVEL ; Low ; - ; count[7] ;
; POWER_UP_LEVEL ; Low ; - ; count[8] ;
+----------------+-------+------+----------+
+----------------------------------------+
; Source assignments for DDS1:u1 ;
+----------------+-------+------+--------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; Low ; - ; P7B[6] ;
+----------------+-------+------+--------+
+----------------------------------------------------------------------------------------------------------+
; Source assignments for DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------------+
+--------------------------------------+
; Source assignments for PL_DPSK2:u2 ;
+----------------+-------+------+------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+------+
; POWER_UP_LEVEL ; Low ; - ; q[0] ;
; POWER_UP_LEVEL ; Low ; - ; q[1] ;
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