Simulator report for dds
Mon Jun 25 10:43:11 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ALTSYNCRAM
  6. Coverage Summary
  7. Complete 1/0-Value Coverage
  8. Missing 1-Value Coverage
  9. Missing 0-Value Coverage
 10. Simulator INI Usage
 11. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 300.0 us     ;
; Simulation Netlist Size     ; 65 nodes     ;
; Simulation Coverage         ;      92.50 % ;
; Total Number of Transitions ; 187853       ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone      ;
; Device                      ; EP1C12Q240C8 ;
+-----------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------------+
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      92.50 % ;
; Total nodes checked                                 ; 65           ;
; Total output ports checked                          ; 80           ;
; Total output ports with complete 1/0-value coverage ; 74           ;
; Total output ports with no 1/0-value coverage       ; 5            ;
; Total output ports with no 1-value coverage         ; 6            ;
; Total output ports with no 0-value coverage         ; 5            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                     ; Output Port Name                                                                              ; Output Port Type ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; portadataout0    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[1] ; portadataout1    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[2] ; portadataout2    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; portadataout3    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; portadataout4    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; portadataout5    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; portadataout6    ;
; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; |DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; portadataout7    ;
; |DDS|DDS1:u1|q[1]                                                                             ; |DDS|DDS1:u1|q[1]~41                                                                          ; cout0            ;
; |DDS|DDS1:u1|q[1]                                                                             ; |DDS|DDS1:u1|q[1]~41COUT1_51                                                                  ; cout1            ;