?? dds.tan.rpt
字號:
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 170.62 MHz ( period = 5.861 ns ) ; DDS1:u1|P7B[6] ; DDS1:u1|REG7B:u5|DOUT[6] ; CLK ; CLK ; None ; None ; 1.046 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[7] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg6 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg0 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg1 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg2 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg3 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg4 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|ram_block1a0~porta_address_reg5 ; DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; 4.319 ns ;
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