LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS                                     -- 頂層設計
    PORT (     CLK : IN  STD_LOGIC;
                dds_out:out std_logic_vector(7 downto 0);
                 dc_out:out std_logic; 
                count1:out std_logic_vector(8 downto 0) ;
                ls:in std_logic ;         --接收端解調輸出的信號
                din1:out std_logic
               );                --發送端輸入的信號
 END;
ARCHITECTURE one OF DDS IS
component ps7 is
port(clk:in std_logic;
load:in std_logic;
 q:out std_logic;
count1:out std_logic_vector(8 downto 0) );
end component;
component dds1            
PORT (     CLK : IN  STD_LOGIC;
               dds_out:out std_logic_vector(7 downto 0);
          din :in std_logic);
 END component;
component fangbo IS                                     --將接收到的信號整形成方波
    PORT (     clk : IN  STD_LOGIC; 
              fout : in STD_LOGIC_VECTOR(7 DOWNTO 0);
                 y : out std_logic );
    end component fangbo;
component pl_dpsk2
port (clk    :in std_logic;          --系統時鐘
     x    :in std_logic;       --方波輸入信號
     y    :out std_logic);     --絕對碼輸出信號
end component PL_DPSK2;
signal r_dds:std_logic_VECTOR(7 DOWNTO 0);--基于DDS的2PSK信號
signal r_fb: STD_LOGIC; --將DDS整形后的方波信號
signal din :std_logic;
begin
u0:ps7 port map(clk,ls,din,count1);
u1:dds1 port map(clk,r_dds,din);    --發送端產生DDS的2PSK信號
u2:pl_dpsk2 port map(clk,r_fb,dc_out); --將整形后的方波信號解調
u3:fangbo port map(clk=>clk,fout=>r_dds,y=>r_fb);--將發送端產生的DDS信號整形成方波
dds_out<=r_dds;din1<=din;
end;