LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fangbo IS                                     --將dds信號整形成方波
    PORT (     clk : IN  STD_LOGIC; 
             fout  : in STD_LOGIC_VECTOR(7 DOWNTO 0);
                 y:out std_logic );
end fangbo;
architecture one of fangbo is
signal fout1,fout2: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal yy:std_logic;

begin
	y<=yy;
	process(clk,fout)
	begin
	if clk 'event  and  clk='1' then
		fout1<=fout;fout2<=fout1;--寄存前1、2、3個時鐘周期的幅度信號
		if  fout2(7)=fout1(7) and fout2(7)=fout(7)  then yy<=fout(7);
		    --當連續三個抽樣點的值大于（或小于）"1000000000"時，方波波形才作改變
		    --保證整形后輸出的方波沒有毛刺出現
		end if;
	end if;
	end process;
end one;