?? altsyncram_kna2.tdf
字號:
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 10,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 10,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 1023,
PORT_B_LOGICAL_RAM_DEPTH = 1024,
PORT_B_LOGICAL_RAM_WIDTH = 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block3a6 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./LUT10X10.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 10,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 10,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 1023,
PORT_B_LOGICAL_RAM_DEPTH = 1024,
PORT_B_LOGICAL_RAM_WIDTH = 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block3a7 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./LUT10X10.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 10,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 10,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 1023,
PORT_B_LOGICAL_RAM_DEPTH = 1024,
PORT_B_LOGICAL_RAM_WIDTH = 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block3a8 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./LUT10X10.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 10,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 10,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 8,
PORT_B_LAST_ADDRESS = 1023,
PORT_B_LOGICAL_RAM_DEPTH = 1024,
PORT_B_LOGICAL_RAM_WIDTH = 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block3a9 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./LUT10X10.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 10,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 1023,
PORT_A_LOGICAL_RAM_DEPTH = 1024,
PORT_A_LOGICAL_RAM_WIDTH = 10,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 10,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 9,
PORT_B_LAST_ADDRESS = 1023,
PORT_B_LOGICAL_RAM_DEPTH = 1024,
PORT_B_LOGICAL_RAM_WIDTH = 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
data_a[9..0] : NODE;
wren_a : NODE;
BEGIN
ram_block3a[9..0].clk0 = clock0;
ram_block3a[9..0].clk1 = clock1;
ram_block3a[0].portaaddr[] = ( address_a[9..0]);
ram_block3a[1].portaaddr[] = ( address_a[9..0]);
ram_block3a[2].portaaddr[] = ( address_a[9..0]);
ram_block3a[3].portaaddr[] = ( address_a[9..0]);
ram_block3a[4].portaaddr[] = ( address_a[9..0]);
ram_block3a[5].portaaddr[] = ( address_a[9..0]);
ram_block3a[6].portaaddr[] = ( address_a[9..0]);
ram_block3a[7].portaaddr[] = ( address_a[9..0]);
ram_block3a[8].portaaddr[] = ( address_a[9..0]);
ram_block3a[9].portaaddr[] = ( address_a[9..0]);
ram_block3a[0].portadatain[] = ( data_a[0..0]);
ram_block3a[1].portadatain[] = ( data_a[1..1]);
ram_block3a[2].portadatain[] = ( data_a[2..2]);
ram_block3a[3].portadatain[] = ( data_a[3..3]);
ram_block3a[4].portadatain[] = ( data_a[4..4]);
ram_block3a[5].portadatain[] = ( data_a[5..5]);
ram_block3a[6].portadatain[] = ( data_a[6..6]);
ram_block3a[7].portadatain[] = ( data_a[7..7]);
ram_block3a[8].portadatain[] = ( data_a[8..8]);
ram_block3a[9].portadatain[] = ( data_a[9..9]);
ram_block3a[9..0].portawe = wren_a;
ram_block3a[0].portbaddr[] = ( address_b[9..0]);
ram_block3a[1].portbaddr[] = ( address_b[9..0]);
ram_block3a[2].portbaddr[] = ( address_b[9..0]);
ram_block3a[3].portbaddr[] = ( address_b[9..0]);
ram_block3a[4].portbaddr[] = ( address_b[9..0]);
ram_block3a[5].portbaddr[] = ( address_b[9..0]);
ram_block3a[6].portbaddr[] = ( address_b[9..0]);
ram_block3a[7].portbaddr[] = ( address_b[9..0]);
ram_block3a[8].portbaddr[] = ( address_b[9..0]);
ram_block3a[9].portbaddr[] = ( address_b[9..0]);
ram_block3a[0].portbdatain[] = ( data_b[0..0]);
ram_block3a[1].portbdatain[] = ( data_b[1..1]);
ram_block3a[2].portbdatain[] = ( data_b[2..2]);
ram_block3a[3].portbdatain[] = ( data_b[3..3]);
ram_block3a[4].portbdatain[] = ( data_b[4..4]);
ram_block3a[5].portbdatain[] = ( data_b[5..5]);
ram_block3a[6].portbdatain[] = ( data_b[6..6]);
ram_block3a[7].portbdatain[] = ( data_b[7..7]);
ram_block3a[8].portbdatain[] = ( data_b[8..8]);
ram_block3a[9].portbdatain[] = ( data_b[9..9]);
ram_block3a[9..0].portbrewe = wren_b;
data_a[] = VCC;
q_a[] = ( ram_block3a[9..0].portadataout[0..0]);
q_b[] = ( ram_block3a[9..0].portbdataout[0..0]);
wren_a = GND;
END;
--VALID FILE
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