?? dds.sim.vwf

?? 利用VHDL語言實現在
?? VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 300000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("CLK")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("dc_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dds_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dds_out[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("dds_out[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dds_out";
}

SIGNAL("ls")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("count1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 9;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("count1[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("count1[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "count1";
}

SIGNAL("fangbo:u3|fout1[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("fangbo:u3|fout2[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("PL_DPSK2:u2|xx1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("PL_DPSK2:u2|xx2")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("PL_DPSK2:u2|y")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("DDS1:u1|q")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 9;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("DDS1:u1|q[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

SIGNAL("DDS1:u1|q[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "DDS1:u1|q";
}

TRANSITION_LIST("CLK")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 7500;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
	}
}

TRANSITION_LIST("dc_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 20550.765;
		LEVEL 1 FOR 40960.0;
		LEVEL 0 FOR 40960.0;
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 61440.0;
		LEVEL 1 FOR 81920.0;
		LEVEL 0 FOR 20480.0;
		LEVEL 1 FOR 13209.235;
	}
}

TRANSITION_LIST("dds_out[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 70.971;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 40.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		LEVEL 1 FOR 1240.0;
		LEVEL 0 FOR 2600.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		LEVEL 1 FOR 1240.0;
		LEVEL 0 FOR 40.0;
		NODE
		{
			REPEAT = 23;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		LEVEL 1 FOR 1240.0;
		LEVEL 0 FOR 2600.0;
		NODE
		{
			REPEAT = 31;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 40.0;
			NODE
			{
				REPEAT = 7;
				LEVEL 1 FOR 1240.0;
				LEVEL 0 FOR 1320.0;
			}
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 2600.0;
			NODE
			{
				REPEAT = 7;
				LEVEL 1 FOR 1240.0;
				LEVEL 0 FOR 1320.0;
			}
		}
		NODE
		{
			REPEAT = 8;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		LEVEL 1 FOR 1240.0;
		LEVEL 0 FOR 40.0;
		NODE
		{
			REPEAT = 9;
			LEVEL 1 FOR 1240.0;
			LEVEL 0 FOR 1320.0;
		}
		LEVEL 1 FOR 329.029;
	}
}

TRANSITION_LIST("dds_out[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 110.907;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 440.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 23;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 440.0;
		NODE
		{
			REPEAT = 31;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 440.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 440.0;
		NODE
		{
			REPEAT = 15;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 840.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 9;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 840.0;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 840.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 129.093;
	}
}

TRANSITION_LIST("dds_out[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 110.875;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 600.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 600.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 120.0;
12 3 4 5 下一頁
?? 文件大小 288 K
?? 上傳用戶 yhb71181491615
?? 所屬分類 VHDL/FPGA/Verilog
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?? dds.sim.vwf

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