|DDS
CLK => fangbo:u3.clk
CLK => pl_dpsk2:u2.clk
CLK => dds1:u1.CLK
CLK => ps7:u0.clk
dds_out[0] <= dds1:u1.dds_out[0]
dds_out[1] <= dds1:u1.dds_out[1]
dds_out[2] <= dds1:u1.dds_out[2]
dds_out[3] <= dds1:u1.dds_out[3]
dds_out[4] <= dds1:u1.dds_out[4]
dds_out[5] <= dds1:u1.dds_out[5]
dds_out[6] <= dds1:u1.dds_out[6]
dds_out[7] <= dds1:u1.dds_out[7]
dc_out <= pl_dpsk2:u2.y
count1[0] <= ps7:u0.count1[0]
count1[1] <= ps7:u0.count1[1]
count1[2] <= ps7:u0.count1[2]
count1[3] <= ps7:u0.count1[3]
count1[4] <= ps7:u0.count1[4]
count1[5] <= ps7:u0.count1[5]
count1[6] <= ps7:u0.count1[6]
count1[7] <= ps7:u0.count1[7]
count1[8] <= ps7:u0.count1[8]
ls => ps7:u0.load
din1 <= ps7:u0.q


|DDS|ps7:u0
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
load => q~reg0.ALOAD
load => c0.PRESET
load => c1.ACLR
load => c2.ACLR
load => c3.PRESET
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
count1[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
count1[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
count1[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
count1[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
count1[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
count1[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
count1[7] <= count[7].DB_MAX_OUTPUT_PORT_TYPE
count1[8] <= count[8].DB_MAX_OUTPUT_PORT_TYPE


|DDS|DDS1:u1
CLK => REG7B:u5.LOAD
CLK => SIN_ROM:u3.clock
CLK => REG7B:u2.LOAD
CLK => q[0].CLK
CLK => q[1].CLK
CLK => q[2].CLK
CLK => q[3].CLK
CLK => q[4].CLK
CLK => q[5].CLK
CLK => q[6].CLK
CLK => q[7].CLK
CLK => q[8].CLK
dds_out[0] <= SIN_ROM:u3.q[0]
dds_out[1] <= SIN_ROM:u3.q[1]
dds_out[2] <= SIN_ROM:u3.q[2]
dds_out[3] <= SIN_ROM:u3.q[3]
dds_out[4] <= SIN_ROM:u3.q[4]
dds_out[5] <= SIN_ROM:u3.q[5]
dds_out[6] <= SIN_ROM:u3.q[6]
dds_out[7] <= SIN_ROM:u3.q[7]
din => P7B[6].ENA


|DDS|DDS1:u1|ADDER7B:u1
A[0] => Add0.IN7
A[1] => Add0.IN6
A[2] => Add0.IN5
A[3] => Add0.IN4
A[4] => Add0.IN3
A[5] => Add0.IN2
A[6] => Add0.IN1
B[0] => Add0.IN14
B[1] => Add0.IN13
B[2] => Add0.IN12
B[3] => Add0.IN11
B[4] => Add0.IN10
B[5] => Add0.IN9
B[6] => Add0.IN8
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|DDS1:u1|REG7B:u2
Load => DOUT[0]~reg0.CLK
Load => DOUT[1]~reg0.CLK
Load => DOUT[2]~reg0.CLK
Load => DOUT[3]~reg0.CLK
Load => DOUT[4]~reg0.CLK
Load => DOUT[5]~reg0.CLK
Load => DOUT[6]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DIN[4] => DOUT[4]~reg0.DATAIN
DIN[5] => DOUT[5]~reg0.DATAIN
DIN[6] => DOUT[6]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|DDS1:u1|sin_rom:u3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_hq21:auto_generated.address_a[0]
address_a[1] => altsyncram_hq21:auto_generated.address_a[1]
address_a[2] => altsyncram_hq21:auto_generated.address_a[2]
address_a[3] => altsyncram_hq21:auto_generated.address_a[3]
address_a[4] => altsyncram_hq21:auto_generated.address_a[4]
address_a[5] => altsyncram_hq21:auto_generated.address_a[5]
address_a[6] => altsyncram_hq21:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hq21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hq21:auto_generated.q_a[0]
q_a[1] <= altsyncram_hq21:auto_generated.q_a[1]
q_a[2] <= altsyncram_hq21:auto_generated.q_a[2]
q_a[3] <= altsyncram_hq21:auto_generated.q_a[3]
q_a[4] <= altsyncram_hq21:auto_generated.q_a[4]
q_a[5] <= altsyncram_hq21:auto_generated.q_a[5]
q_a[6] <= altsyncram_hq21:auto_generated.q_a[6]
q_a[7] <= altsyncram_hq21:auto_generated.q_a[7]
q_b[0] <= <GND>


|DDS|DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|DDS|DDS1:u1|ADDER7B:u4
A[0] => Add0.IN7
A[1] => Add0.IN6
A[2] => Add0.IN5
A[3] => Add0.IN4
A[4] => Add0.IN3
A[5] => Add0.IN2
A[6] => Add0.IN1
B[0] => Add0.IN14
B[1] => Add0.IN13
B[2] => Add0.IN12
B[3] => Add0.IN11
B[4] => Add0.IN10
B[5] => Add0.IN9
B[6] => Add0.IN8
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|DDS1:u1|REG7B:u5
Load => DOUT[0]~reg0.CLK
Load => DOUT[1]~reg0.CLK
Load => DOUT[2]~reg0.CLK
Load => DOUT[3]~reg0.CLK
Load => DOUT[4]~reg0.CLK
Load => DOUT[5]~reg0.CLK
Load => DOUT[6]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DIN[4] => DOUT[4]~reg0.DATAIN
DIN[5] => DOUT[5]~reg0.DATAIN
DIN[6] => DOUT[6]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|PL_DPSK2:u2
clk => y~reg0.CLK
clk => xx2.CLK
clk => xx1.CLK
clk => q[0].CLK
clk => q[1].CLK
clk => q[2].CLK
clk => q[3].CLK
clk => q[4].CLK
clk => q[5].CLK
clk => q[6].CLK
clk => q[7].CLK
clk => q[8].CLK
x => xx1.DATAIN
y <= y~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|fangbo:u3
clk => yy.CLK
clk => fout2[7].CLK
clk => fout1[7].CLK
fout[0] => ~NO_FANOUT~
fout[1] => ~NO_FANOUT~
fout[2] => ~NO_FANOUT~
fout[3] => ~NO_FANOUT~
fout[4] => ~NO_FANOUT~
fout[5] => ~NO_FANOUT~
fout[6] => ~NO_FANOUT~
fout[7] => process0~1.IN1
fout[7] => fout1[7].DATAIN
fout[7] => yy.DATAIN
y <= yy.DB_MAX_OUTPUT_PORT_TYPE