LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER7B IS
    PORT (  A : IN  STD_LOGIC_VECTOR(6 DOWNTO 0);
            B : IN  STD_LOGIC_VECTOR(6 DOWNTO 0);
            S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)     );
END ADDER7B;
ARCHITECTURE behav OF ADDER7B IS
    BEGIN
	S <= A + B;
END behav;